Patch by Josef Wagner, 04 Jun 2004:

- DDR Ram support for PM520 (MPC5200)
- support for different flash types (PM520)
- USB / IDE / CF-Card / DiskOnChip support for PM520
- 8 bit boot rom support for PM520/CE520
- Add auto SDRAM module detection for MicroSys CPC45 board (MPC8245)
- I2C and RTC support for CPC45
- support of new flash type (28F160C3T) for CPC45

1 files changed, 211 insertions, 193 deletions

diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h
index 66f978e..5a00133 100644
--- a/include/configs/CPC45.h
+++ b/include/configs/CPC45.h
@@ -59,10 +59,13 @@
 #define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
-				CFG_CMD_BEDBUG  | \
+				CFG_CMD_BEDBUG	| \
+				CFG_CMD_DATE	| \
 				CFG_CMD_DHCP	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_I2C	| \
 				CFG_CMD_PCI	| \
-				0 /* CFG_CMD_DATE */	)
+				CFG_CMD_SDRAM	)
 
 /* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
  */
@@ -77,17 +80,17 @@
 #define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 
 #if 1
-#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
 #endif
 #ifdef	CFG_HUSH_PARSER
-#define	CFG_PROMPT_HUSH_PS2	"> "
+#define CFG_PROMPT_HUSH_PS2	"> "
 #endif
 
 /* Print Buffer Size
  */
 #define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
 
-#define	CFG_MAXARGS	16		/* max number of command args	*/
+#define CFG_MAXARGS	16		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 #define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/
 
@@ -97,29 +100,29 @@
  * Please note that CFG_SDRAM_BASE _must_ start at 0
  */
 
-#define CFG_SDRAM_BASE	    0x00000000
+#define CFG_SDRAM_BASE		0x00000000
 
 #if defined(CONFIG_BOOT_ROM)
-#define CFG_FLASH_BASE	    0xFF000000
+#define CFG_FLASH_BASE		0xFF000000
 #else
-#define CFG_FLASH_BASE	    0xFF800000
+#define CFG_FLASH_BASE		0xFF800000
 #endif
 
-#define CFG_RESET_ADDRESS   0xFFF00100
+#define CFG_RESET_ADDRESS	0xFFF00100
 
-#define CFG_EUMB_ADDR	    0xFCE00000
+#define CFG_EUMB_ADDR		0xFCE00000
 
-#define CFG_MONITOR_BASE    TEXT_BASE
+#define CFG_MONITOR_BASE	TEXT_BASE
 
-#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
-#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
 
-#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
-#define CFG_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
+#define CFG_MEMTEST_START	0x00004000	/* memtest works on		*/
+#define CFG_MEMTEST_END		0x02000000	/* 0 ... 32 MB in DRAM		*/
 
-	/* Maximum amount of RAM.
-	 */
-#define CFG_MAX_RAM_SIZE    0x10000000
+/* Maximum amount of RAM.
+ */
+#define CFG_MAX_RAM_SIZE	0x10000000
 
 
 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
@@ -133,13 +136,13 @@
  * Definitions for initial stack pointer and data area
  */
 
-	/* Size in bytes reserved for initial data
-	 */
-#define CFG_GBL_DATA_SIZE    128
+/* Size in bytes reserved for initial data
+ */
+#define CFG_GBL_DATA_SIZE	128
 
-#define CFG_INIT_RAM_ADDR     0x40000000
-#define CFG_INIT_RAM_END      0x1000
-#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_RAM_ADDR	0x40000000
+#define CFG_INIT_RAM_END	0x1000
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 
 /*
  * NS16550 Configuration
@@ -153,7 +156,30 @@
 
 #define CFG_NS16550_COM1	(CFG_EUMB_ADDR + 0x4500)
 #define CFG_NS16550_COM2	(CFG_EUMB_ADDR + 0x4600)
-#define	DUART_DCR		(CFG_EUMB_ADDR + 0x4511)
+#define DUART_DCR		(CFG_EUMB_ADDR + 0x4511)
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+
+#define CFG_I2C_SPEED		100000 /* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_PCF8563
+#define CFG_I2C_RTC_ADDR	0x51
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR		0x58
+#define CFG_I2C_EEPROM_ADDR_LEN		1
+#define CFG_EEPROM_PAGE_WRITE_BITS	4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
 
 /*
  * Low Level Configuration Settings
@@ -162,62 +188,49 @@
  * For the detail description refer to the MPC8240 user's manual.
  */
 
-#define CONFIG_SYS_CLK_FREQ  33000000
-#define CFG_HZ		     1000
-/*
- * SDRAM Configuration Settings
- * Please note: currently only 64 and 128 MB SDRAM size supported
- * set CFG_SDRAM_SIZE to 64 or 128
- * Memory configuration using SPD information stored on the SODIMMs
- * not yet supported.
- */
+#define CONFIG_SYS_CLK_FREQ	33000000
+#define CFG_HZ			1000
 
-#define	CFG_SDRAM_SIZE    64		/* SDRAM size -- 64 or 128 MB supported */
 
-	/* Bit-field values for MCCR1.
-	 */
-#define CFG_ROMNAL	    0
-#define CFG_ROMFAL	    7
+/* Bit-field values for MCCR1.
+ */
+#define CFG_ROMNAL		0
+#define CFG_ROMFAL		8
+
+#define CFG_BANK0_ROW		0	/* SDRAM bank 7-0 row address */
+#define CFG_BANK1_ROW		0
+#define CFG_BANK2_ROW		0
+#define CFG_BANK3_ROW		0
+#define CFG_BANK4_ROW		0
+#define CFG_BANK5_ROW		0
+#define CFG_BANK6_ROW		0
+#define CFG_BANK7_ROW		0
+
+/* Bit-field values for MCCR2.
+ */
 
-#if (CFG_SDRAM_SIZE == 64)			/* 64 MB */
-#define CFG_BANK0_ROW	0			/* SDRAM bank 7-0 row address */
-#elif (CFG_SDRAM_SIZE == 128)			/* 128 MB */
-#define CFG_BANK0_ROW	2			/* SDRAM bank 7-0 row address */
-#else
-#  error "SDRAM size not supported"
-#endif
-#define CFG_BANK1_ROW	0
-#define CFG_BANK2_ROW	0
-#define CFG_BANK3_ROW	0
-#define CFG_BANK4_ROW	0
-#define CFG_BANK5_ROW	0
-#define CFG_BANK6_ROW	0
-#define CFG_BANK7_ROW	0
-
-	/* Bit-field values for MCCR2.
-	 */
-#define CFG_REFINT	    430	    /* Refresh interval			*/
+#define CFG_REFINT		0x2ec
 
-	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
-	 */
-#define CFG_BSTOPRE	    192
+/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
+ */
+#define CFG_BSTOPRE		160
 
-	/* Bit-field values for MCCR3.
-	 */
-#define CFG_REFREC	    2	    /* Refresh to activate interval	*/
-#define CFG_RDLAT	    3	    /* Data latancy from read command	*/
+/* Bit-field values for MCCR3.
+ */
+#define CFG_REFREC		2	/* Refresh to activate interval		*/
+#define CFG_RDLAT		0	/* Data latancy from read command	*/
 
-	/* Bit-field values for MCCR4.
-	 */
-#define CFG_PRETOACT	    2	    /* Precharge to activate interval	*/
-#define CFG_ACTTOPRE	    5	    /* Activate to Precharge interval	*/
-#define CFG_SDMODE_CAS_LAT  2	    /* SDMODE CAS latancy		*/
-#define CFG_SDMODE_WRAP	    0	    /* SDMODE wrap type			*/
-#define CFG_SDMODE_BURSTLEN 2	    /* SDMODE Burst length		*/
-#define CFG_ACTORW	    2
+/* Bit-field values for MCCR4.
+ */
+#define CFG_PRETOACT		2	/* Precharge to activate interval	*/
+#define CFG_ACTTOPRE		5	/* Activate to Precharge interval	*/
+#define CFG_SDMODE_CAS_LAT	2	/* SDMODE CAS latancy			*/
+#define CFG_SDMODE_WRAP		0	/* SDMODE wrap type			*/
+#define CFG_SDMODE_BURSTLEN	2	/* SDMODE Burst length			*/
+#define CFG_ACTORW		2
 #define CFG_REGISTERD_TYPE_BUFFER 1
-#define CFG_EXTROM	    1
-#define CFG_REGDIMM	    0
+#define CFG_EXTROM		0
+#define CFG_REGDIMM		0
 
 /* Memory bank settings.
  * Only bits 20-29 are actually used from these vales to set the
@@ -226,32 +239,35 @@
  * address. Refer to the MPC8240 book.
  */
 
-#define CFG_BANK0_START	    0x00000000
-#define CFG_BANK0_END	    (CFG_MAX_RAM_SIZE - 1)
-#define CFG_BANK0_ENABLE    1
-#define CFG_BANK1_START	    0x3ff00000
-#define CFG_BANK1_END	    0x3fffffff
-#define CFG_BANK1_ENABLE    0
-#define CFG_BANK2_START	    0x3ff00000
-#define CFG_BANK2_END	    0x3fffffff
-#define CFG_BANK2_ENABLE    0
-#define CFG_BANK3_START	    0x3ff00000
-#define CFG_BANK3_END	    0x3fffffff
-#define CFG_BANK3_ENABLE    0
-#define CFG_BANK4_START	    0x3ff00000
-#define CFG_BANK4_END	    0x3fffffff
-#define CFG_BANK4_ENABLE    0
-#define CFG_BANK5_START	    0x3ff00000
-#define CFG_BANK5_END	    0x3fffffff
-#define CFG_BANK5_ENABLE    0
-#define CFG_BANK6_START	    0x3ff00000
-#define CFG_BANK6_END	    0x3fffffff
-#define CFG_BANK6_ENABLE    0
-#define CFG_BANK7_START	    0x3ff00000
-#define CFG_BANK7_END	    0x3fffffff
-#define CFG_BANK7_ENABLE    0
-
-#define CFG_ODCR	    0xff
+#define CFG_BANK0_START		0x00000000
+#define CFG_BANK0_END		(CFG_MAX_RAM_SIZE - 1)
+#define CFG_BANK0_ENABLE	1
+#define CFG_BANK1_START		0x3ff00000
+#define CFG_BANK1_END		0x3fffffff
+#define CFG_BANK1_ENABLE	0
+#define CFG_BANK2_START		0x3ff00000
+#define CFG_BANK2_END		0x3fffffff
+#define CFG_BANK2_ENABLE	0
+#define CFG_BANK3_START		0x3ff00000
+#define CFG_BANK3_END		0x3fffffff
+#define CFG_BANK3_ENABLE	0
+#define CFG_BANK4_START		0x3ff00000
+#define CFG_BANK4_END		0x3fffffff
+#define CFG_BANK4_ENABLE	0
+#define CFG_BANK5_START		0x3ff00000
+#define CFG_BANK5_END		0x3fffffff
+#define CFG_BANK5_ENABLE	0
+#define CFG_BANK6_START		0x3ff00000
+#define CFG_BANK6_END		0x3fffffff
+#define CFG_BANK6_ENABLE	0
+#define CFG_BANK7_START		0x3ff00000
+#define CFG_BANK7_END		0x3fffffff
+#define CFG_BANK7_ENABLE	0
+
+#define CFG_ODCR		0xff
+#define CFG_PGMAX		0x32	/* how long the 8240 retains the	*/
+					/* currently accessed page in memory	*/
+					/* see 8240 book for details		*/
 
 #define CFG_IBAT0L  (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 #define CFG_IBAT0U  (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
@@ -279,7 +295,7 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
@@ -295,7 +311,7 @@
 	 */
 #define CFG_ENV_IS_IN_FLASH	    1
 
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x7C0000)
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x7F8000)
 #define CFG_ENV_SIZE		0x4000	/* Size of the Environment		*/
 #define CFG_ENV_OFFSET		0	/* starting right at the beginning	*/
 #define CFG_ENV_SECT_SIZE	0x8000 /* Size of the Environment Sector	*/
@@ -317,118 +333,118 @@
 #define BOOTFLAG_WARM		0x02	/* Software reboot			*/
 
 
-#define	SRAM_BASE		0x80000000	/* SRAM base address 	*/
-#define	SRAM_END		0x801FFFFF
+#define SRAM_BASE		0x80000000	/* SRAM base address	*/
+#define SRAM_END		0x801FFFFF
 
-/*---------------------------------------------------------------------*/
-/* CPC45 Memory Map                                                    */
-/*---------------------------------------------------------------------*/
-#define	SRAM_BASE	0x80000000	/* SRAM base address            */
-#define	ST16552_A_BASE	0x80200000	/* ST16552 channel A		*/
-#define	ST16552_B_BASE	0x80400000	/* ST16552 channel A		*/
-#define	BCSR_BASE	0x80600000	/* board control / status registers */
-#define	DISPLAY_BASE	0x80600040	/* DISPLAY base			*/
-#define	PCMCIA_MEM_BASE	0x81000000	/* PCMCIA memory window base        */
-#define	PCMCIA_IO_BASE	0xFE000000	/* PCMCIA IO window base            */
+/*----------------------------------------------------------------------*/
+/* CPC45 Memory Map							*/
+/*----------------------------------------------------------------------*/
+#define SRAM_BASE	0x80000000	/* SRAM base address		*/
+#define ST16552_A_BASE	0x80200000	/* ST16552 channel A		*/
+#define ST16552_B_BASE	0x80400000	/* ST16552 channel A		*/
+#define BCSR_BASE	0x80600000	/* board control / status registers */
+#define DISPLAY_BASE	0x80600040	/* DISPLAY base			*/
+#define PCMCIA_MEM_BASE 0x81000000	/* PCMCIA memory window base	*/
+#define PCMCIA_IO_BASE	0xFE000000	/* PCMCIA IO window base	*/
 
 
 /*---------------------------------------------------------------------*/
-/* CPC45 Control/Status Registers                                      */
+/* CPC45 Control/Status Registers				       */
 /*---------------------------------------------------------------------*/
-#define	IRQ_ENA_1		*((volatile uchar*)(BCSR_BASE + 0x00))
-#define	IRQ_STAT_1		*((volatile uchar*)(BCSR_BASE + 0x01))
-#define	IRQ_ENA_2		*((volatile uchar*)(BCSR_BASE + 0x02))
-#define	IRQ_STAT_2		*((volatile uchar*)(BCSR_BASE + 0x03))
-#define	BOARD_CTRL		*((volatile uchar*)(BCSR_BASE + 0x04))
-#define	BOARD_STAT		*((volatile uchar*)(BCSR_BASE + 0x05))
-#define	WDG_START		*((volatile uchar*)(BCSR_BASE + 0x06))
-#define	WDG_PRESTOP		*((volatile uchar*)(BCSR_BASE + 0x06))
-#define	WDG_STOP		*((volatile uchar*)(BCSR_BASE + 0x06))
-#define	BOARD_REV		*((volatile uchar*)(BCSR_BASE + 0x07))
+#define IRQ_ENA_1		*((volatile uchar*)(BCSR_BASE + 0x00))
+#define IRQ_STAT_1		*((volatile uchar*)(BCSR_BASE + 0x01))
+#define IRQ_ENA_2		*((volatile uchar*)(BCSR_BASE + 0x02))
+#define IRQ_STAT_2		*((volatile uchar*)(BCSR_BASE + 0x03))
+#define BOARD_CTRL		*((volatile uchar*)(BCSR_BASE + 0x04))
+#define BOARD_STAT		*((volatile uchar*)(BCSR_BASE + 0x05))
+#define WDG_START		*((volatile uchar*)(BCSR_BASE + 0x06))
+#define WDG_PRESTOP		*((volatile uchar*)(BCSR_BASE + 0x06))
+#define WDG_STOP		*((volatile uchar*)(BCSR_BASE + 0x06))
+#define BOARD_REV		*((volatile uchar*)(BCSR_BASE + 0x07))
 
 /* IRQ_ENA_1 bit definitions */
-#define	I_ENA_1_IERA	0x80		/* INTA enable 			*/
-#define	I_ENA_1_IERB	0x40		/* INTB enable			*/
-#define	I_ENA_1_IERC	0x20		/* INTC enable			*/
-#define	I_ENA_1_IERD	0x10		/* INTD enable			*/
+#define I_ENA_1_IERA	0x80		/* INTA enable			*/
+#define I_ENA_1_IERB	0x40		/* INTB enable			*/
+#define I_ENA_1_IERC	0x20		/* INTC enable			*/
+#define I_ENA_1_IERD	0x10		/* INTD enable			*/
 
 /* IRQ_STAT_1 bit definitions */
-#define	I_STAT_1_INTA	0x80		/* INTA status			*/
-#define	I_STAT_1_INTB	0x40		/* INTB status			*/
-#define	I_STAT_1_INTC	0x20		/* INTC status			*/
-#define	I_STAT_1_INTD	0x10		/* INTD status			*/
+#define I_STAT_1_INTA	0x80		/* INTA status			*/
+#define I_STAT_1_INTB	0x40		/* INTB status			*/
+#define I_STAT_1_INTC	0x20		/* INTC status			*/
+#define I_STAT_1_INTD	0x10		/* INTD status			*/
 
 /* IRQ_ENA_2 bit definitions */
-#define	I_ENA_2_IEAB	0x80		/* ABORT IRQ enable		*/
-#define	I_ENA_2_IEK1	0x40		/* KEY1 IRQ enable		*/
-#define	I_ENA_2_IEK2	0x20		/* KEY2 IRQ enable		*/
-#define	I_ENA_2_IERT	0x10		/* RTC IRQ enable		*/
-#define	I_ENA_2_IESM	0x08		/* LM81 IRQ enable		*/
-#define	I_ENA_2_IEDG	0x04		/* DEGENERATING IRQ enable	*/
-#define	I_ENA_2_IES2	0x02		/* ST16552/B IRQ enable		*/
-#define	I_ENA_2_IES1	0x01		/* ST16552/A IRQ enable		*/
+#define I_ENA_2_IEAB	0x80		/* ABORT IRQ enable		*/
+#define I_ENA_2_IEK1	0x40		/* KEY1 IRQ enable		*/
+#define I_ENA_2_IEK2	0x20		/* KEY2 IRQ enable		*/
+#define I_ENA_2_IERT	0x10		/* RTC IRQ enable		*/
+#define I_ENA_2_IESM	0x08		/* LM81 IRQ enable		*/
+#define I_ENA_2_IEDG	0x04		/* DEGENERATING IRQ enable	*/
+#define I_ENA_2_IES2	0x02		/* ST16552/B IRQ enable		*/
+#define I_ENA_2_IES1	0x01		/* ST16552/A IRQ enable		*/
 
 /* IRQ_STAT_2 bit definitions */
-#define	I_STAT_2_ABO	0x80		/* ABORT IRQ status		*/
-#define	I_STAT_2_KY1	0x40		/* KEY1 IRQ status		*/
-#define	I_STAT_2_KY2	0x20		/* KEY2 IRQ status		*/
-#define	I_STAT_2_RTC	0x10		/* RTC IRQ status		*/
-#define	I_STAT_2_SMN	0x08		/* LM81 IRQ status		*/
-#define	I_STAT_2_DEG	0x04		/* DEGENERATING IRQ status	*/
-#define	I_STAT_2_SIO2	0x02		/* ST16552/B IRQ status		*/
-#define	I_STAT_2_SIO1	0x01		/* ST16552/A IRQ status		*/
+#define I_STAT_2_ABO	0x80		/* ABORT IRQ status		*/
+#define I_STAT_2_KY1	0x40		/* KEY1 IRQ status		*/
+#define I_STAT_2_KY2	0x20		/* KEY2 IRQ status		*/
+#define I_STAT_2_RTC	0x10		/* RTC IRQ status		*/
+#define I_STAT_2_SMN	0x08		/* LM81 IRQ status		*/
+#define I_STAT_2_DEG	0x04		/* DEGENERATING IRQ status	*/
+#define I_STAT_2_SIO2	0x02		/* ST16552/B IRQ status		*/
+#define I_STAT_2_SIO1	0x01		/* ST16552/A IRQ status		*/
 
 /* BOARD_CTRL bit definitions */
-#define	USER_LEDS		2			/* 2 user LEDs	*/
+#define USER_LEDS		2			/* 2 user LEDs	*/
 
 #if (USER_LEDS == 4)
-#define	B_CTRL_WRSE		0x80
-#define	B_CTRL_KRSE		0x40
-#define	B_CTRL_FWRE		0x20		/* Flash write enable		*/
-#define	B_CTRL_FWPT		0x10		/* Flash write protect		*/
-#define	B_CTRL_LED3		0x08		/* LED 3 control		*/
-#define	B_CTRL_LED2		0x04		/* LED 2 control		*/
-#define	B_CTRL_LED1		0x02		/* LED 1 control		*/
-#define	B_CTRL_LED0		0x01		/* LED 0 control		*/
+#define B_CTRL_WRSE		0x80
+#define B_CTRL_KRSE		0x40
+#define B_CTRL_FWRE		0x20		/* Flash write enable		*/
+#define B_CTRL_FWPT		0x10		/* Flash write protect		*/
+#define B_CTRL_LED3		0x08		/* LED 3 control		*/
+#define B_CTRL_LED2		0x04		/* LED 2 control		*/
+#define B_CTRL_LED1		0x02		/* LED 1 control		*/
+#define B_CTRL_LED0		0x01		/* LED 0 control		*/
 #else
-#define	B_CTRL_WRSE		0x80
-#define	B_CTRL_KRSE		0x40
-#define	B_CTRL_FWRE_1		0x20		/* Flash write enable		*/
-#define	B_CTRL_FWPT_1		0x10		/* Flash write protect		*/
-#define	B_CTRL_LED1		0x08		/* LED 1 control		*/
-#define	B_CTRL_LED0		0x04		/* LED 0 control		*/
-#define	B_CTRL_FWRE_0		0x02		/* Flash write enable		*/
-#define	B_CTRL_FWPT_0		0x01		/* Flash write protect		*/
+#define B_CTRL_WRSE		0x80
+#define B_CTRL_KRSE		0x40
+#define B_CTRL_FWRE_1		0x20		/* Flash write enable		*/
+#define B_CTRL_FWPT_1		0x10		/* Flash write protect		*/
+#define B_CTRL_LED1		0x08		/* LED 1 control		*/
+#define B_CTRL_LED0		0x04		/* LED 0 control		*/
+#define B_CTRL_FWRE_0		0x02		/* Flash write enable		*/
+#define B_CTRL_FWPT_0		0x01		/* Flash write protect		*/
 #endif
 
 /* BOARD_STAT bit definitions */
-#define	B_STAT_WDGE		0x80
-#define	B_STAT_WDGS		0x40
-#define	B_STAT_WRST		0x20
-#define	B_STAT_KRST		0x10
-#define	B_STAT_CSW3		0x08		/* sitch bit 3 status		*/
-#define	B_STAT_CSW2		0x04		/* sitch bit 2 status		*/
-#define	B_STAT_CSW1		0x02		/* sitch bit 1 status		*/
-#define	B_STAT_CSW0		0x01		/* sitch bit 0 status		*/
+#define B_STAT_WDGE		0x80
+#define B_STAT_WDGS		0x40
+#define B_STAT_WRST		0x20
+#define B_STAT_KRST		0x10
+#define B_STAT_CSW3		0x08		/* sitch bit 3 status		*/
+#define B_STAT_CSW2		0x04		/* sitch bit 2 status		*/
+#define B_STAT_CSW1		0x02		/* sitch bit 1 status		*/
+#define B_STAT_CSW0		0x01		/* sitch bit 0 status		*/
 
 /*---------------------------------------------------------------------*/
-/* Display addresses                                                   */
+/* Display addresses						       */
 /*---------------------------------------------------------------------*/
-#define	DISP_UDC_RAM	(DISPLAY_BASE + 0x08)	/* UDC RAM	       */
-#define	DISP_CHR_RAM	(DISPLAY_BASE + 0x18)	/* character Ram       */
-#define	DISP_FLASH	(DISPLAY_BASE + 0x20)	/* Flash Ram           */
+#define DISP_UDC_RAM	(DISPLAY_BASE + 0x08)	/* UDC RAM	       */
+#define DISP_CHR_RAM	(DISPLAY_BASE + 0x18)	/* character Ram       */
+#define DISP_FLASH	(DISPLAY_BASE + 0x20)	/* Flash Ram	       */
 
-#define	DISP_UDC_ADR	*((volatile uchar*)(DISPLAY_BASE + 0x00))	/* UDC Address Reg.    */
-#define	DISP_CWORD	*((volatile uchar*)(DISPLAY_BASE + 0x10))	/* Control Word Reg.   */
+#define DISP_UDC_ADR	*((volatile uchar*)(DISPLAY_BASE + 0x00))	/* UDC Address Reg.    */
+#define DISP_CWORD	*((volatile uchar*)(DISPLAY_BASE + 0x10))	/* Control Word Reg.   */
 
-#define	DISP_DIG0	*((volatile uchar*)(DISP_CHR_RAM + 0x00))	/* Digit 0 address     */
-#define	DISP_DIG1	*((volatile uchar*)(DISP_CHR_RAM + 0x01))	/* Digit 0 address     */
-#define	DISP_DIG2	*((volatile uchar*)(DISP_CHR_RAM + 0x02))	/* Digit 0 address     */
-#define	DISP_DIG3	*((volatile uchar*)(DISP_CHR_RAM + 0x03))	/* Digit 0 address     */
-#define	DISP_DIG4	*((volatile uchar*)(DISP_CHR_RAM + 0x04))	/* Digit 0 address     */
-#define	DISP_DIG5	*((volatile uchar*)(DISP_CHR_RAM + 0x05))	/* Digit 0 address     */
-#define	DISP_DIG6	*((volatile uchar*)(DISP_CHR_RAM + 0x06))	/* Digit 0 address     */
-#define	DISP_DIG7	*((volatile uchar*)(DISP_CHR_RAM + 0x07))	/* Digit 0 address     */
+#define DISP_DIG0	*((volatile uchar*)(DISP_CHR_RAM + 0x00))	/* Digit 0 address     */
+#define DISP_DIG1	*((volatile uchar*)(DISP_CHR_RAM + 0x01))	/* Digit 0 address     */
+#define DISP_DIG2	*((volatile uchar*)(DISP_CHR_RAM + 0x02))	/* Digit 0 address     */
+#define DISP_DIG3	*((volatile uchar*)(DISP_CHR_RAM + 0x03))	/* Digit 0 address     */
+#define DISP_DIG4	*((volatile uchar*)(DISP_CHR_RAM + 0x04))	/* Digit 0 address     */
+#define DISP_DIG5	*((volatile uchar*)(DISP_CHR_RAM + 0x05))	/* Digit 0 address     */
+#define DISP_DIG6	*((volatile uchar*)(DISP_CHR_RAM + 0x06))	/* Digit 0 address     */
+#define DISP_DIG7	*((volatile uchar*)(DISP_CHR_RAM + 0x07))	/* Digit 0 address     */
 
 
 /*-----------------------------------------------------------------------
@@ -436,14 +452,16 @@
  *-----------------------------------------------------------------------
  */
 #define CONFIG_PCI			/* include pci support			*/
-#undef CONFIG_PCI_PNP
+#undef	CONFIG_PCI_PNP
+#undef	CONFIG_PCI_SCAN_SHOW
 
-#define CONFIG_NET_MULTI		/* Multi ethernet cards support 	*/
+#define CONFIG_NET_MULTI		/* Multi ethernet cards support		*/
 
 #define CONFIG_EEPRO100
-#define CFG_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
+#define CFG_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
 
-#define PCI_ENET0_IOADDR	0x00104000
+#define PCI_ENET0_IOADDR	0x82000000
 #define PCI_ENET0_MEMADDR	0x82000000
-#define	PCI_PLX9030_MEMADDR	0x82100000
+#define PCI_PLX9030_IOADDR	0x82100000
+#define PCI_PLX9030_MEMADDR	0x82100000
 #endif	/* __CONFIG_H */