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| author | Marian Balakowicz <m8@semihalf.com> | 2006-04-08 19:08:06 +0200 |
|---|---|---|
| committer | Marian Balakowicz <m8@semihalf.com> | 2006-04-08 19:08:06 +0200 |
| commit | 6db39708117d6391a72f3fc3ea7860231b630270 (patch) | |
| tree | 1c69fc84c3f615fe60217096c2947744c72e3528 /include/configs/CATcenter.h | |
| parent | 2fc000d756920b340945a74ec1214a34d9e84858 (diff) | |
| download | u-boot-imx-6db39708117d6391a72f3fc3ea7860231b630270.zip u-boot-imx-6db39708117d6391a72f3fc3ea7860231b630270.tar.gz u-boot-imx-6db39708117d6391a72f3fc3ea7860231b630270.tar.bz2 | |
Fix JFFS2 support for legacy NAND driver.
Some more NAND cleanup and small fixes.
Diffstat (limited to 'include/configs/CATcenter.h')
| -rw-r--r-- | include/configs/CATcenter.h | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h index ffe89cb..7ec4599 100644 --- a/include/configs/CATcenter.h +++ b/include/configs/CATcenter.h @@ -193,6 +193,8 @@ */ #define CFG_NAND0_BASE 0xFF400000 #define CFG_NAND1_BASE 0xFF000000 +#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE } +#define NAND_BIG_DELAY_US 25 /* For CATcenter there is only NAND on the module */ #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ @@ -218,9 +220,9 @@ #define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */ -#define NAND_DISABLE_CE(nand) do \ +#define MACRO_NAND_DISABLE_CE(nandptr) do \ { \ - switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \ + switch((unsigned long)nandptr) \ { \ case CFG_NAND0_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \ @@ -231,9 +233,9 @@ } \ } while(0) -#define NAND_ENABLE_CE(nand) do \ +#define MACRO_NAND_ENABLE_CE(nandptr) do \ { \ - switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \ + switch((unsigned long)nandptr) \ { \ case CFG_NAND0_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \ @@ -244,8 +246,7 @@ } \ } while(0) - -#define NAND_CTL_CLRALE(nandptr) do \ +#define MACRO_NAND_CTL_CLRALE(nandptr) do \ { \ switch((unsigned long)nandptr) \ { \ @@ -258,7 +259,7 @@ } \ } while(0) -#define NAND_CTL_SETALE(nandptr) do \ +#define MACRO_NAND_CTL_SETALE(nandptr) do \ { \ switch((unsigned long)nandptr) \ { \ @@ -271,7 +272,7 @@ } \ } while(0) -#define NAND_CTL_CLRCLE(nandptr) do \ +#define MACRO_NAND_CTL_CLRCLE(nandptr) do \ { \ switch((unsigned long)nandptr) \ { \ @@ -284,7 +285,7 @@ } \ } while(0) -#define NAND_CTL_SETCLE(nandptr) do { \ +#define MACRO_NAND_CTL_SETCLE(nandptr) do { \ switch((unsigned long)nandptr) { \ case CFG_NAND0_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \ |