* The PS/2 mux on the BMS2003 board needs 450 ms after power on

  before we can access it; add delay in case we are faster (with no
  CF card inserted)

* Cleanup of some init functions

* Make sure SCC Ethernet is always stopped by the time we boot Linux
  to avoid Linux crashes by early packets coming in.

* Accelerate flash accesses on LWMON board by using buffered writes

1 files changed, 44 insertions, 44 deletions

diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h
index 7aceb58..21bc441 100644
--- a/include/configs/CANBT.h
+++ b/include/configs/CANBT.h
@@ -34,12 +34,12 @@
  */
 
 #define CONFIG_405CR		1	/* This is a PPC405CR CPU	*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family   */
-#define CONFIG_CANBT		1	/* ...on a CANBT board	        */
+#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
+#define CONFIG_CANBT		1	/* ...on a CANBT board		*/
 
-#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 
-#define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */
+#define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_BOOTDELAY	1	/* autoboot after 1 seconds	*/
@@ -52,13 +52,13 @@
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
-#undef  CONFIG_PCI_PNP			/* no pci plug-and-play		*/
+#undef	CONFIG_PCI_PNP			/* no pci plug-and-play		*/
 
-#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
 
-#define CONFIG_COMMANDS	     (( CONFIG_CMD_DFL	|       \
-				CFG_CMD_IRQ	|       \
-				CFG_CMD_EEPROM      ) & \
+#define CONFIG_COMMANDS	     (( CONFIG_CMD_DFL	|	\
+				CFG_CMD_IRQ	|	\
+				CFG_CMD_EEPROM	    ) & \
 			       ~CFG_CMD_NET)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@@ -66,7 +66,7 @@
 
 #undef CONFIG_WATCHDOG			/* watchdog disabled		*/
 
-#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
 /*
  * Miscellaneous configurable options
@@ -74,30 +74,30 @@
 #define CFG_LONGHELP			/* undef to save memory		*/
 #define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 #define CFG_MAXARGS	16		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
 
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define CFG_EXT_SERIAL_CLOCK    14745600 /* use external serial clock   */
+#define CFG_EXT_SERIAL_CLOCK	14745600 /* use external serial clock	*/
 
 /* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE      \
+#define CFG_BAUDRATE_TABLE	\
 	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 	 57600, 115200, 230400, 460800, 921600 }
 
 #define CFG_LOAD_ADDR	0x100000	/* default load address */
 #define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */
 
-#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/
+#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
@@ -127,44 +127,44 @@
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
-#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
-#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
-#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
+#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
 /*
  * The following defines are added for buggy IOP480 byte interface.
  * All other boards should use the standard values (CPCI405 etc.)
  */
-#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
-#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
-#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
+#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
 
-#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
 #if 0 /* Use FLASH for environment variables */
 
-#define	CFG_ENV_IS_IN_FLASH	1
-#define CFG_ENV_OFFSET		0x00010000	/* Offset of Environment Sector	*/
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_OFFSET		0x00010000	/* Offset of Environment Sector */
 #define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
 
-#define CFG_ENV_SECT_SIZE	0x10000	/* see README - env sector total size	*/
+#define CFG_ENV_SECT_SIZE	0x10000 /* see README - env sector total size	*/
 
 #else /* Use EEPROM for environment variables */
 
-#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE            0x400   /* 1024 bytes may be used for env vars */
+#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars */
 				   /* total size of a CAT24WC08 is 1024 bytes */
 #endif
 
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC08) for environment
  */
-#define CONFIG_HARD_I2C                 /* I2C with hardware support */
+#define CONFIG_HARD_I2C			/* I2C with hardware support */
 #define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CFG_I2C_SLAVE		0x7F
 
 #define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CFG_I2C_EEPROM_ADDR_LEN	1	/* bytes of address		*/
+#define CFG_I2C_EEPROM_ADDR_LEN 1	/* bytes of address		*/
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
 #define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
 
@@ -190,26 +190,26 @@
  * External Bus Controller (EBC) Setup
  */
 
-/* Memory Bank 0 (Flash Bank 0) initialization                                  */
-#define CFG_EBC_PB0AP           0x92015480
-#define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CFG_EBC_PB0AP		0x92015480
+#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
-/* Memory Bank 1 (CAN/USB) initialization                                       */
-#define CFG_EBC_PB1AP           0x010053C0  /* enable Ready, BEM=1              */
-#define CFG_EBC_PB1CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 1 (CAN/USB) initialization					*/
+#define CFG_EBC_PB1AP		0x010053C0  /* enable Ready, BEM=1		*/
+#define CFG_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 2 (Misc-IO/LEDs) initialization                                  */
-#define CFG_EBC_PB2AP           0x000004c0  /* no Ready, BEM=1                  */
-#define CFG_EBC_PB2CR           0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit  */
+/* Memory Bank 2 (Misc-IO/LEDs) initialization					*/
+#define CFG_EBC_PB2AP		0x000004c0  /* no Ready, BEM=1			*/
+#define CFG_EBC_PB2CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
 
-/* Memory Bank 3 (CAN Features) initialization                                  */
-#define CFG_EBC_PB3AP           0x80000040  /* no Ready, BEM=1                  */
-#define CFG_EBC_PB3CR           0xF021C000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=32bit */
+/* Memory Bank 3 (CAN Features) initialization					*/
+#define CFG_EBC_PB3AP		0x80000040  /* no Ready, BEM=1			*/
+#define CFG_EBC_PB3CR		0xF021C000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=32bit */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in RAM)
  */
-#define CFG_INIT_RAM_ADDR	0x00ef0000 /* inside of SDRAM                   */
+#define CFG_INIT_RAM_ADDR	0x00ef0000 /* inside of SDRAM			*/
 #define CFG_INIT_RAM_END	0x0f00	/* End of used area in RAM	       */
 #define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)