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authorShaveta Leekha <shaveta@freescale.com>2014-11-12 16:00:22 +0530
committerYork Sun <yorksun@freescale.com>2014-12-05 08:06:12 -0800
commitf1d8074c08d77270f9117427768874be05b4be94 (patch)
treeb03730bf3b676cb868d9808380d3c8ed4c813bfc /include/configs/B4860QDS.h
parentffc1a87b915054e58d5157fb7804961024809b24 (diff)
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B4860QDS: SGMII related updates
- Enable SGMII support for 0x8d Serdes 2 protocol. - Correct Phy address for DTSECx for 0x8d/0xb2 Serdes 2 protocol. - Updated debug statement - Add Alternate LC VCO protocols(0x8d-->0x8c, 0xb2-->0xb1) - Rename onboard PHY address defines for more readability - Add these new Defines in B4860QDS.h file Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'include/configs/B4860QDS.h')
-rw-r--r--include/configs/B4860QDS.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index dc1a9bc..b47b9de 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -713,8 +713,8 @@ unsigned long get_board_ddr_clk(void);
#endif /* CONFIG_PCI */
#ifdef CONFIG_FMAN_ENET
-#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10
-#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11
+#define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
+#define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
/*B4860 QDS AMC2PEX-2S default PHY_ADDR */
#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/