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| author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-05-30 14:45:06 +0200 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-05-30 14:45:06 +0200 |
| commit | a19b0dd62d7b8efc658fa1aa685ff5665878f3ee (patch) | |
| tree | 1fadf0fb3da83203ba28f209ec99e1b33e03f4d5 /include/configs/B4860QDS.h | |
| parent | 60985bba58e7695dac1fddae8cdbb62d8cfd1254 (diff) | |
| parent | a71d45d706a5b51c348160163b6c159632273fed (diff) | |
| download | u-boot-imx-a19b0dd62d7b8efc658fa1aa685ff5665878f3ee.zip u-boot-imx-a19b0dd62d7b8efc658fa1aa685ff5665878f3ee.tar.gz u-boot-imx-a19b0dd62d7b8efc658fa1aa685ff5665878f3ee.tar.bz2 | |
Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
common/cmd_fpga.c
drivers/usb/host/ohci-at91.c
Diffstat (limited to 'include/configs/B4860QDS.h')
| -rw-r--r-- | include/configs/B4860QDS.h | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index b09119a..1c9d08e 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -36,7 +36,6 @@ /* High Level Configuration Options */ #define CONFIG_BOOKE -#define CONFIG_E6500 #define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ @@ -528,6 +527,15 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SF_DEFAULT_MODE 0 /* + * MAPLE + */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull +#else +#define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000 +#endif + +/* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ @@ -623,7 +631,11 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_FMAN_ENET #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10 #define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11 -#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 + +/*B4860 QDS AMC2PEX-2S default PHY_ADDR */ +#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ +#define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ + #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d |