Merge 'next' branch

Conflicts:

	board/freescale/mpc8536ds/mpc8536ds.c
	include/configs/mgcoge.h

Signed-off-by: Wolfgang Denk <wd@denx.de>

1 files changed, 97 insertions, 97 deletions

diff --git a/include/configs/Alaska8220.h b/include/configs/Alaska8220.h
index 431ed4e..2581fdf 100644
--- a/include/configs/Alaska8220.h
+++ b/include/configs/Alaska8220.h
@@ -35,8 +35,8 @@
 
 /* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
    determine the CPU speed. */
-#define CFG_MPC8220_CLKIN	30000000/* ... running at 30MHz */
-#define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
+#define CONFIG_SYS_MPC8220_CLKIN	30000000/* ... running at 30MHz */
+#define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	*/
@@ -53,16 +53,16 @@
 
 #ifdef CONFIG_EXTUART_CONSOLE
 #   define CONFIG_CONS_INDEX	1
-#   define CFG_NS16550_SERIAL
-#   define CFG_NS16550
-#   define CFG_NS16550_REG_SIZE 1
-#   define CFG_NS16550_COM1	(CFG_CPLD_BASE + 0x1008)
-#   define CFG_NS16550_CLK	18432000
+#   define CONFIG_SYS_NS16550_SERIAL
+#   define CONFIG_SYS_NS16550
+#   define CONFIG_SYS_NS16550_REG_SIZE 1
+#   define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CPLD_BASE + 0x1008)
+#   define CONFIG_SYS_NS16550_CLK	18432000
 #endif
 
 #define CONFIG_BAUDRATE		115200	    /* ... at 115200 bps */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 #define CONFIG_TIMESTAMP			/* Print image info with timestamp */
 
@@ -120,104 +120,104 @@
  * I2C configuration
  */
 #define CONFIG_HARD_I2C		1
-#define CFG_I2C_MODULE		1
+#define CONFIG_SYS_I2C_MODULE		1
 
-#define CFG_I2C_SPEED		100000 /* 100 kHz */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 
 /*
  * EEPROM configuration
  */
-#define CFG_I2C_EEPROM_ADDR		0x52	/* 1011000xb */
-#define CFG_I2C_EEPROM_ADDR_LEN		1
-#define CFG_EEPROM_PAGE_WRITE_BITS	3
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x52	/* 1011000xb */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70
 /*
 #define CONFIG_ENV_IS_IN_EEPROM	1
 #define CONFIG_ENV_OFFSET		0
 #define CONFIG_ENV_SIZE		256
 */
 
-/* If CFG_AMD_BOOT is defined, the the system will boot from AMD.
+/* If CONFIG_SYS_AMD_BOOT is defined, the the system will boot from AMD.
    else undefined it will boot from Intel Strata flash */
-#define CFG_AMD_BOOT		1
+#define CONFIG_SYS_AMD_BOOT		1
 
 /*
  * Flexbus Chipselect configuration
  */
-#if defined (CFG_AMD_BOOT)
-#define CFG_CS0_BASE		0xfff0
-#define CFG_CS0_MASK		0x00080000  /* 512 KB */
-#define CFG_CS0_CTRL		0x003f0d40
-
-#define CFG_CS1_BASE		0xfe00
-#define CFG_CS1_MASK		0x01000000  /* 16 MB */
-#define CFG_CS1_CTRL		0x003f1540
+#if defined (CONFIG_SYS_AMD_BOOT)
+#define CONFIG_SYS_CS0_BASE		0xfff0
+#define CONFIG_SYS_CS0_MASK		0x00080000  /* 512 KB */
+#define CONFIG_SYS_CS0_CTRL		0x003f0d40
+
+#define CONFIG_SYS_CS1_BASE		0xfe00
+#define CONFIG_SYS_CS1_MASK		0x01000000  /* 16 MB */
+#define CONFIG_SYS_CS1_CTRL		0x003f1540
 #else
-#define CFG_CS0_BASE		0xff00
-#define CFG_CS0_MASK		0x01000000  /* 16 MB */
-#define CFG_CS0_CTRL		0x003f1540
+#define CONFIG_SYS_CS0_BASE		0xff00
+#define CONFIG_SYS_CS0_MASK		0x01000000  /* 16 MB */
+#define CONFIG_SYS_CS0_CTRL		0x003f1540
 
-#define CFG_CS1_BASE		0xfe08
-#define CFG_CS1_MASK		0x00080000  /* 512 KB */
-#define CFG_CS1_CTRL		0x003f0d40
+#define CONFIG_SYS_CS1_BASE		0xfe08
+#define CONFIG_SYS_CS1_MASK		0x00080000  /* 512 KB */
+#define CONFIG_SYS_CS1_CTRL		0x003f0d40
 #endif
 
-#define CFG_CS2_BASE		0xf100
-#define CFG_CS2_MASK		0x00040000
-#define CFG_CS2_CTRL		0x003f1140
+#define CONFIG_SYS_CS2_BASE		0xf100
+#define CONFIG_SYS_CS2_MASK		0x00040000
+#define CONFIG_SYS_CS2_CTRL		0x003f1140
 
-#define CFG_CS3_BASE		0xf200
-#define CFG_CS3_MASK		0x00040000
-#define CFG_CS3_CTRL		0x003f1100
+#define CONFIG_SYS_CS3_BASE		0xf200
+#define CONFIG_SYS_CS3_MASK		0x00040000
+#define CONFIG_SYS_CS3_CTRL		0x003f1100
 
 
-#define CFG_FLASH0_BASE		(CFG_CS0_BASE << 16)
-#define CFG_FLASH1_BASE		(CFG_CS1_BASE << 16)
+#define CONFIG_SYS_FLASH0_BASE		(CONFIG_SYS_CS0_BASE << 16)
+#define CONFIG_SYS_FLASH1_BASE		(CONFIG_SYS_CS1_BASE << 16)
 
-#if defined (CFG_AMD_BOOT)
-#define CFG_AMD_BASE		CFG_FLASH0_BASE
-#define CFG_INTEL_BASE		CFG_FLASH1_BASE + 0xf00000
-#define CFG_FLASH_BASE		CFG_AMD_BASE
+#if defined (CONFIG_SYS_AMD_BOOT)
+#define CONFIG_SYS_AMD_BASE		CONFIG_SYS_FLASH0_BASE
+#define CONFIG_SYS_INTEL_BASE		CONFIG_SYS_FLASH1_BASE + 0xf00000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_AMD_BASE
 #else
-#define CFG_INTEL_BASE		CFG_FLASH0_BASE + 0xf00000
-#define CFG_AMD_BASE		CFG_FLASH1_BASE
-#define CFG_FLASH_BASE		CFG_INTEL_BASE
+#define CONFIG_SYS_INTEL_BASE		CONFIG_SYS_FLASH0_BASE + 0xf00000
+#define CONFIG_SYS_AMD_BASE		CONFIG_SYS_FLASH1_BASE
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_INTEL_BASE
 #endif
 
-#define CFG_CPLD_BASE		(CFG_CS2_BASE << 16)
-#define CFG_FPGA_BASE		(CFG_CS3_BASE << 16)
+#define CONFIG_SYS_CPLD_BASE		(CONFIG_SYS_CS2_BASE << 16)
+#define CONFIG_SYS_FPGA_BASE		(CONFIG_SYS_CS3_BASE << 16)
 
 
-#define CFG_MAX_FLASH_BANKS	4	/* max num of memory banks	*/
-#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	4	/* max num of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
 
-#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
-#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
-#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
-#define CFG_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+#define CONFIG_SYS_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
 
 #define PHYS_AMD_SECT_SIZE	0x00010000 /*  64 KB sectors (x2) */
 #define PHYS_INTEL_SECT_SIZE	0x00020000 /* 128 KB sectors (x2) */
 
-#define CFG_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_CHECKSUM
 /*
  * Environment settings
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#if defined (CFG_AMD_BOOT)
-#define CONFIG_ENV_ADDR		(CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_AMD_SECT_SIZE)
+#if defined (CONFIG_SYS_AMD_BOOT)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_AMD_SECT_SIZE)
 #define CONFIG_ENV_SIZE		PHYS_AMD_SECT_SIZE
 #define CONFIG_ENV_SECT_SIZE	PHYS_AMD_SECT_SIZE
-#define CONFIG_ENV1_ADDR		(CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_INTEL_SECT_SIZE)
+#define CONFIG_ENV1_ADDR		(CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_INTEL_SECT_SIZE)
 #define CONFIG_ENV1_SIZE		PHYS_INTEL_SECT_SIZE
 #define CONFIG_ENV1_SECT_SIZE	PHYS_INTEL_SECT_SIZE
 #else
-#define CONFIG_ENV_ADDR		(CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_INTEL_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_INTEL_SECT_SIZE)
 #define CONFIG_ENV_SIZE		PHYS_INTEL_SECT_SIZE
 #define CONFIG_ENV_SECT_SIZE	PHYS_INTEL_SECT_SIZE
-#define CONFIG_ENV1_ADDR		(CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_AMD_SECT_SIZE)
+#define CONFIG_ENV1_ADDR		(CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_AMD_SECT_SIZE)
 #define CONFIG_ENV1_SIZE		PHYS_AMD_SECT_SIZE
 #define CONFIG_ENV1_SECT_SIZE	PHYS_AMD_SECT_SIZE
 #endif
@@ -238,37 +238,37 @@
 /*
  * Memory map
  */
-#define CFG_MBAR		0xF0000000
-#define CFG_SDRAM_BASE		0x00000000
-#define CFG_DEFAULT_MBAR	0x80000000
-#define CFG_SRAM_BASE		(CFG_MBAR + 0x20000)
-#define CFG_SRAM_SIZE		0x8000
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_SRAM_BASE		(CONFIG_SYS_MBAR + 0x20000)
+#define CONFIG_SYS_SRAM_SIZE		0x8000
 
 /* Use SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR	(CFG_MBAR + 0x20000)
-#define CFG_INIT_RAM_END	0x8000	/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MBAR + 0x20000)
+#define CONFIG_SYS_INIT_RAM_END	0x8000	/* End of used area in DPRAM */
 
-#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-#   define CFG_RAMBOOT		1
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
 #endif
 
-#define CFG_MONITOR_LEN		(256 << 10) /* Reserve 256 kB for Monitor   */
-#define CFG_MALLOC_LEN		(128 << 10) /* Reserve 128 kB for malloc()  */
-#define CFG_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10) /* Reserve 256 kB for Monitor   */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10) /* Reserve 128 kB for malloc()  */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */
 
 /* SDRAM configuration */
-#define CFG_SDRAM_TOTAL_BANKS		2
-#define CFG_SDRAM_SPD_I2C_ADDR		0x51		/* 7bit */
-#define CFG_SDRAM_SPD_SIZE		0x40
-#define CFG_SDRAM_CAS_LATENCY		4		/* (CL=2)x2 */
+#define CONFIG_SYS_SDRAM_TOTAL_BANKS		2
+#define CONFIG_SYS_SDRAM_SPD_I2C_ADDR		0x51		/* 7bit */
+#define CONFIG_SYS_SDRAM_SPD_SIZE		0x40
+#define CONFIG_SYS_SDRAM_CAS_LATENCY		4		/* (CL=2)x2 */
 
 /* SDRAM drive strength register */
-#define CFG_SDRAM_DRIVE_STRENGTH	((DRIVE_STRENGTH_LOW  << SDRAMDS_SBE_SHIFT) | \
+#define CONFIG_SYS_SDRAM_DRIVE_STRENGTH	((DRIVE_STRENGTH_LOW  << SDRAMDS_SBE_SHIFT) | \
 					 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
 					 (DRIVE_STRENGTH_LOW  << SDRAMDS_SBA_SHIFT) | \
 					 (DRIVE_STRENGTH_OFF  << SDRAMDS_SBS_SHIFT) | \
@@ -285,34 +285,34 @@
 /*
  * Miscellaneous configurable options
  */
-#define CFG_LONGHELP			    /* undef to save memory	*/
-#define CFG_PROMPT		"=> "	    /* Monitor Command Prompt	*/
+#define CONFIG_SYS_LONGHELP			    /* undef to save memory	*/
+#define CONFIG_SYS_PROMPT		"=> "	    /* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CBSIZE		1024	    /* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		1024	    /* Console I/O Buffer Size	*/
 #else
-#define CFG_CBSIZE		256	    /* Console I/O Buffer Size	*/
+#define CONFIG_SYS_CBSIZE		256	    /* Console I/O Buffer Size	*/
 #endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
-#define CFG_MAXARGS		16	    /* max number of command args   */
-#define CFG_BARGSIZE		CFG_CBSIZE  /* Boot Argument Buffer Size    */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	    /* max number of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size    */
 
-#define CFG_MEMTEST_START	0x00100000  /* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000  /* 1 ... 15 MB in DRAM  */
+#define CONFIG_SYS_MEMTEST_START	0x00100000  /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000  /* 1 ... 15 MB in DRAM  */
 
-#define CFG_LOAD_ADDR		0x100000    /* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000    /* default load address */
 
-#define CFG_HZ			1000	    /* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ			1000	    /* decrementer freq: 1 ms ticks */
 
-#define CFG_CACHELINE_SIZE	32	/* For MPC8220 CPUs */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8220 CPUs */
 #if defined(CONFIG_CMD_KGDB)
-#  define CFG_CACHELINE_SHIFT	5   /* log base 2 of the above value */
+#  define CONFIG_SYS_CACHELINE_SHIFT	5   /* log base 2 of the above value */
 #endif
 
 /*
  * Various low-level settings
  */
-#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL		HID0_ICE
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
 
 /*
  * JFFS2 partitions