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authorwdenk <wdenk>2003-07-17 23:16:40 +0000
committerwdenk <wdenk>2003-07-17 23:16:40 +0000
commit2535d60277cc295adf75cd5721dcecd840c69a63 (patch)
treea4a7c42580ded1e631658cec4f7a26d8e677a342 /include/configs/ADS860.h
parent945af8d723a29e9b6289d84250745ed0dc16fc81 (diff)
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* Patch by Martin Krause, 17 Jul 2003:
add delay to get I2C working with "imm" command and s3c24x0_i2c.c * Patch by Richard Woodruff, 17 July 03: - Fixed bug in OMAP1510 baud rate divisor settings. * Patch by Nye Liu, 16 July 2003: MPC860FADS fixes: - add MPC86xADS support (uses MPC86xADS.h) - add 866P/T core support (also MPC859T/MPC859DSL/MPC852T) o PLPRCR changes o BRG changes (EXTAL/XTAL restricted to 10MHz) o don't trust gclk() software measurement by default, depend on CONFIG_8xx_GCLK_FREQ - add DRAM SIMM not installed detection - use more "correct" SDRAM initialization sequence - allow different SDRAM sizes (8xxADS has 8M) - default DER is 0 - remove unused MAMR defines from FADS860T.h (all done in fads.c) - rename MAMR/MBMR defines to be more consistent. Should eventually be merged into MxMR to better reflect the PowerQUICC datasheet. * Patch by Yuli Barcohen, 16 Jul 2003: support new Motorola PQ2FADS-ZU evaluation board which replaced MPC8260ADS and MPC8266ADS
Diffstat (limited to 'include/configs/ADS860.h')
-rw-r--r--include/configs/ADS860.h11
1 files changed, 7 insertions, 4 deletions
diff --git a/include/configs/ADS860.h b/include/configs/ADS860.h
index 1b73692..0045303 100644
--- a/include/configs/ADS860.h
+++ b/include/configs/ADS860.h
@@ -19,6 +19,7 @@
#include <mpc8xx_irq.h>
#define CONFIG_MPC860 1
+#define CONFIG_MPC860T 1
#define CONFIG_ADS 1
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
@@ -31,10 +32,12 @@
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */
#define CFG_I2C_SLAVE 0x7F
-#define MPC8XX_XIN 32768 /* 32.768 kHz input frequency */
-#define MPC8XX_FACT 0x5F6 /* Multiply by 1526 */
+#define CFG_8XX_XIN 32768 /* 32.768 kHz input frequency */
+#define CFG_8XX_FACT 0x5F6 /* Multiply by 1526 */
/* MPC8XX_FACT * MPC8XX_XIN = 50 MHz */
+#define CONFIG_8xx_GCLK_FREQ ((CFG_8XX_XIN) * (CFG_8XX_FACT))
+
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
#if 0
@@ -136,7 +139,7 @@
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
@@ -198,7 +201,7 @@
*-----------------------------------------------------------------------
* set the PLL, the low-power modes and the reset control (15-29)
*/
-#define CFG_PLPRCR (((MPC8XX_FACT-1) << 20) | \
+#define CFG_PLPRCR (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
/*-----------------------------------------------------------------------