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authorShaohui Xie <Shaohui.Xie@freescale.com>2012-06-28 23:37:25 +0000
committerAndy Fleming <afleming@freescale.com>2012-08-08 17:13:39 -0500
commit145dbc02501bba43cfee952d5669406c871be6d8 (patch)
treee949391365b2b6728467c2ef41f4a3d67daa6646 /include/common.h
parent98de369b1ca49a3c6d1b6408e78d05cbf2f3ea5d (diff)
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powerpc/p2041: configure the CPLD lane_mux according to RCW
Lane muxing on p2041 is controlled by a reg in CPLD, offset of this reg is 0xc, CPLD supports SATA by default, we should re-configure the lane muxing according to RCW, which indicates what SerDes protocol it is running. Default lane muxing map is as below: Lane G on bank1 routes to SGMII, controlled by bit 1 of the reg; Lane A on bank2 routes to AURORA, controlled by bit 0 of the reg; Lane C/D on bank2 routes to SATA0 and SATA1, controlled by bit 2 and bit 3 respectively. Default value of these bits for lane muxing is '1', we should set or clear these bits accoring to RCW. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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