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author | Anton Vorontsov <avorontsov@ru.mvista.com> | 2008-10-08 20:52:54 +0400 |
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committer | Kim Phillips <kim.phillips@freescale.com> | 2008-10-21 18:34:17 -0500 |
commit | b3379f3fd13969934c00097c05754e7a8990fd39 (patch) | |
tree | ef090d007003684a065c954ba8b7930ef21cb09f /include/clps7111.h | |
parent | 00f7bbae92e3b13f2b37aeb1def9bb12445521b7 (diff) | |
download | u-boot-imx-b3379f3fd13969934c00097c05754e7a8990fd39.zip u-boot-imx-b3379f3fd13969934c00097c05754e7a8990fd39.tar.gz u-boot-imx-b3379f3fd13969934c00097c05754e7a8990fd39.tar.bz2 |
mpc83xx: add ELBC NAND support for the MPC837XEMDS boards
Though NAND chip is replaceable on the MPC837XE-MDS boards, the
current settings don't work with the default chip on the board.
Nevertheless Freescale's U-Boot sets the option register correctly,
so I just dumped the register from the working u-boot. My guess is
that the old settings were applicable for some pilot boards, not
found in the production.
This patch also enables FSL ELBC driver so that we could access
the NAND storage in the u-boot.
The NAND support costs about 45KB, so the u-boot no longer fits
into two 128KB NOR flash sectors, thus we also have to adjust
environment location: add another 128KB to the monitor length.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
It is due to hardware design and logic defect, that is the
I/O[0:7] of NAND chip is connected to LAD[7:0], so when
the NAND chip connected to nLCS3, you have to set up the
OR3[BCTLD] = '1' for normal operation, otherwise it will have
bus contention due to the pin 48/25 of U60 is enabled.
Setup the OR3[BCTLD] = '1' , that meaning the LBCTL is not
asserted upon access to the NAND chip, keep the default state.
Acked-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'include/clps7111.h')
0 files changed, 0 insertions, 0 deletions