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authorAnton Staaf <robotboy@chromium.org>2011-10-17 16:46:13 -0700
committerWolfgang Denk <wd@denx.de>2011-10-23 20:50:43 +0200
commit1e41f5ad455e75d3985a0e4670ba1338c2e8faca (patch)
tree48c3538f33268a49e35268dc9b05416e1995d050 /include/clps7111.h
parent3620f860eff02722aa559e568f4ca87f4c304901 (diff)
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cache: include asm/cache.h for ARCH_DMA_MINALIGN definition
ARCH_DMA_MINALIGN will be used to allocate DMA buffers that are aligned correctly. In all current cases this means that the DMA buffer will be aligned to at least the L1 data cache line size of the configured architecture. If the board configuration file does not specify the architecture L1 data cache line size then the maximum line size of the architecture is used to align DMA buffers. Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Ilya Yanok <yanok@emcraft.com> Cc: Laurence Withers <lwithers@guralp.com>
Diffstat (limited to 'include/clps7111.h')
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