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| author | Sjoerd Simons <sjoerd.simons@collabora.co.uk> | 2015-03-12 22:33:29 +0100 |
|---|---|---|
| committer | Minkyu Kang <mk7.kang@samsung.com> | 2015-04-06 14:21:29 +0900 |
| commit | d7e1f02efc8e5272015afed596c395b5a4f8e196 (patch) | |
| tree | efeb03cade2504edcb4ed5730d7c8af75fa9a4cd /include/clk.h | |
| parent | f44ef7d60c7349c0eed5d2363a2649badaae2610 (diff) | |
| download | u-boot-imx-d7e1f02efc8e5272015afed596c395b5a4f8e196.zip u-boot-imx-d7e1f02efc8e5272015afed596c395b5a4f8e196.tar.gz u-boot-imx-d7e1f02efc8e5272015afed596c395b5a4f8e196.tar.bz2 | |
config: peach: Correct memory layout environment settings
The peach boards have their SDRAM start address at 0x20000000 instead of
0x40000000 which seems common for all other exynos5 based boards. This
means the layout set in exynos5-common.h causes the kernel be loaded
more then 128MB (at 0x42000000) away from memory start which breaks
booting kernels with CONFIG_AUTO_ZRELADDR
Define a custom MEM_LAYOUT_ENV_SETTINGS for both peach boards which uses
the same offsets from start of memory as the common exynos5 settings.
This fixes booting via bootz and PXE
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'include/clk.h')
0 files changed, 0 insertions, 0 deletions