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| author | Fabio Estevam <fabio.estevam@freescale.com> | 2015-10-03 14:21:00 -0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-10-12 12:56:32 -0400 |
| commit | f861f51c4673d35908e4e330a86c81d7d909b51c (patch) | |
| tree | 458a3dbe0522d27746ea843e55e94f9ba447b34e /include/bus_vcxk.h | |
| parent | f532727d16ebd3f8f9464aa503a1990f2f3b3211 (diff) | |
| download | u-boot-imx-f861f51c4673d35908e4e330a86c81d7d909b51c.zip u-boot-imx-f861f51c4673d35908e4e330a86c81d7d909b51c.tar.gz u-boot-imx-f861f51c4673d35908e4e330a86c81d7d909b51c.tar.bz2 | |
ls102xa: Fix reset hang
Since commit 623d96e89aca6("imx: wdog: correct wcr register settings")
issuing a 'reset' command causes the system to hang.
Unlike i.MX and Vybrid, the watchdog controller on LS102x is big-endian.
This means that the watchdog on LS1021 has been working by accident as
it does not use the big-endian accessors in drivers/watchdog/imx_watchdog.c.
Commit 623d96e89aca6("imx: wdog: correct wcr register settings") only
revelead the endianness problem on LS102x.
In order to fix the reset hang, introduce a reset_cpu() implementation that
is specific for ls102x, which accesses the watchdog WCR register in big-endian
format. All that is required to reset LS102x is to clear the SRS bit.
This approach is a temporary workaround to avoid a regression for LS102x
in the 2015.10 release. The proper fix is to make the watchdog driver
endian-aware, so that it can work for i.MX, Vybrid and LS102x.
Reported-by: Sinan Akman <sinan@writeme.com>
Tested-by: Sinan Akman <sinan@writeme.com>
Reviewed-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'include/bus_vcxk.h')
0 files changed, 0 insertions, 0 deletions