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authorAjay Kumar <ajaykumar.rs@samsung.com>2015-03-04 19:05:25 +0530
committerMinkyu Kang <mk7.kang@samsung.com>2015-04-06 14:34:40 +0900
commit6102560891d09db79196654aa414afc5acfa7911 (patch)
tree2b1dd6a626e369c4da48d579fb3038b2cbb0de7e /include/bedbug
parent70b4fb660df25d4a150833f7487a0059d1827fee (diff)
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Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panels
The existing setting for rpll_sdiv generates 70.5Mhz RPLL video clock to drive 1366x768 panel on peach_pit. This clock rate is not sufficient to drive 1920x1080 panel on peach-pi. So, we adjust rpll_sdiv to 3 so that it generates 141Mhz pixel clock which can drive peach-pi LCD. This change doesn't break peach-pit LCD since 141/2=70.5Mhz, i.e FIMD divider at IP level will get set to 1(the required divider setting will be calculated and set by exynos_fimd_set_clock()) and hence peach-pit LCD still works fine. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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