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authorNobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>2008-06-06 16:24:13 +0900
committerNobuhiro Iwamatsu <iwamatsu@nigauri.org>2008-06-09 14:20:57 +0900
commit60179098a95eaa972007d7ec58e4c1588029720f (patch)
tree74ba9d4cce89139149ffebe18e4f3858e1a92bac /include/asm-sh/cpu_sh7763.h
parent08c5fabe181d663eec0feba5ecd02c0b78934a52 (diff)
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sh: Add support Renesas SH7763
Renesas SH7763 has 3 SCIF, MMC, LCDC, Ethernet and other. This patch supprts CPU register's header file. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'include/asm-sh/cpu_sh7763.h')
-rw-r--r--include/asm-sh/cpu_sh7763.h51
1 files changed, 51 insertions, 0 deletions
diff --git a/include/asm-sh/cpu_sh7763.h b/include/asm-sh/cpu_sh7763.h
new file mode 100644
index 0000000..78b456b
--- /dev/null
+++ b/include/asm-sh/cpu_sh7763.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2007,2008 Nobuhiro Iwamatsu
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _ASM_CPU_SH7763_H_
+#define _ASM_CPU_SH7763_H_
+
+/* CACHE */
+#define CACHE_OC_NUM_WAYS 1
+#define CCR 0xFF00001C
+#define CCR_CACHE_INIT 0x0000090b
+
+/* SCIF */
+/* SCIF0 */
+#define SCIF0_BASE SCSMR0
+#define SCSMR0 0xFFE00000
+
+/* SCIF1 */
+#define SCIF1_BASE SCSMR1
+#define SCSMR1 0xFFE08000
+
+/* SCIF2 */
+#define SCIF2_BASE SCSMR2
+#define SCSMR2 0xFFE10000
+
+/* Watchdog Timer */
+#define WTCNT WDTST
+#define WDTST 0xFFCC0000
+
+/* TMU */
+#define TSTR 0xFFD80004
+#define TCOR0 0xFFD80008
+#define TCNT0 0xFFD8000C
+#define TCR0 0xFFD80010
+
+#endif /* _ASM_CPU_SH7763_H_ */