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authorWolfgang Denk <wd@denx.de>2008-09-01 00:03:40 +0200
committerWolfgang Denk <wd@denx.de>2008-09-01 00:03:40 +0200
commitde5b094def5d80c4355c0326cfb54b9289f7d609 (patch)
treee1145f02977d099f9dc51174a1c0cd7c58b8d55d /include/asm-sh/cpu_sh7203.h
parent845842c1e4c465c895cdfcd013e162320d127048 (diff)
parentc75e772a2f061a508bba28ded1b5bea91f0442b0 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-sh
Diffstat (limited to 'include/asm-sh/cpu_sh7203.h')
-rw-r--r--include/asm-sh/cpu_sh7203.h41
1 files changed, 41 insertions, 0 deletions
diff --git a/include/asm-sh/cpu_sh7203.h b/include/asm-sh/cpu_sh7203.h
new file mode 100644
index 0000000..77dcac4
--- /dev/null
+++ b/include/asm-sh/cpu_sh7203.h
@@ -0,0 +1,41 @@
+#ifndef _ASM_CPU_SH7203_H_
+#define _ASM_CPU_SH7203_H_
+
+/* Cache */
+#define CCR1 0xFFFC1000
+#define CCR CCR1
+
+/* PFC */
+#define PACR 0xA4050100
+#define PBCR 0xA4050102
+#define PCCR 0xA4050104
+#define PETCR 0xA4050106
+
+/* Port Data Registers */
+#define PADR 0xA4050120
+#define PBDR 0xA4050122
+#define PCDR 0xA4050124
+
+/* BSC */
+
+/* SDRAM controller */
+
+/* SCIF */
+#define SCSMR_0 0xFFFE8000
+#define SCIF0_BASE SCSMR_0
+
+/* Timer(CMT) */
+#define CMSTR 0xFFFEC000
+#define CMCSR_0 0xFFFEC002
+#define CMCNT_0 0xFFFEC004
+#define CMCOR_0 0xFFFEC006
+#define CMCSR_1 0xFFFEC008
+#define CMCNT_1 0xFFFEC00A
+#define CMCOR_1 0xFFFEC00C
+
+/* On chip oscillator circuits */
+#define FRQCR 0xA415FF80
+#define WTCNT 0xA415FF84
+#define WTCSR 0xA415FF86
+
+#endif /* _ASM_CPU_SH7203_H_ */