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| author | Stefan Roese <sr@denx.de> | 2009-09-28 17:33:45 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2009-10-02 13:53:37 +0200 |
| commit | fb95169e39f2d03270bed552d27bbb02627a443e (patch) | |
| tree | c94e691e322097c7cdc43943cd3bb05b3e7c760e /include/asm-ppc | |
| parent | d24bd2517a2b847f773453eab0ee5b1c8ebc74ba (diff) | |
| download | u-boot-imx-fb95169e39f2d03270bed552d27bbb02627a443e.zip u-boot-imx-fb95169e39f2d03270bed552d27bbb02627a443e.tar.gz u-boot-imx-fb95169e39f2d03270bed552d27bbb02627a443e.tar.bz2 | |
ppc4xx: Merge PPC4xx DDR and DDR2 ECC handling
This patch merges the ECC handling (ECC parity byte writing) into one
file (ecc.c) for all PPC4xx SDRAM controllers except for PPC440EPx/GRx.
This exception is because only those PPC's use the completely different
Denali SDRAM controller core.
Previously we had two routines to generate/write the ECC parity bytes.
With this patch we now only have one core function left.
Tested on Kilauea (no ECC) and Katmai (with and without ECC).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Felix Radensky <felix@embedded-sol.com>
Cc: Grant Erickson <gerickson@nuovations.com>
Cc: Pieter Voorthuijsen <pv@prodrive.nl>
Diffstat (limited to 'include/asm-ppc')
| -rw-r--r-- | include/asm-ppc/ppc4xx-sdram.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index b6182d4..92be514 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -117,6 +117,7 @@ #define SDRAM_MCSTS_MRSC 0x80000000 #define SDRAM_MCSTS_SRMS 0x40000000 #define SDRAM_MCSTS_CIS 0x20000000 +#define SDRAM_MCSTS_IDLE_NOT 0x00000000 /* Mem contr not idle */ /* * SDRAM Refresh Timer Register @@ -416,8 +417,7 @@ #define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */ #define SDRAM_MMODE 0x88 /* memory mode */ #define SDRAM_MEMODE 0x89 /* memory extended mode */ -#define SDRAM_ECCCR 0x98 /* ECC error status */ -#define SDRAM_ECCES SDRAM_ECCCR +#define SDRAM_ECCES 0x98 /* ECC error status */ #define SDRAM_CID 0xA4 /* core ID */ #ifndef CONFIG_405EX #define SDRAM_RID 0xA8 /* revision ID */ @@ -1397,7 +1397,6 @@ /* * Prototypes */ -void inline blank_string(int size); inline void ppc4xx_ibm_ddr2_register_dump(void); u32 mfdcr_any(u32); void mtdcr_any(u32, u32); @@ -1405,6 +1404,8 @@ u32 ddr_wrdtr(u32); u32 ddr_clktr(u32); void spd_ddr_init_hang(void); u32 DQS_autocalibration(void); +phys_size_t sdram_memsize(void); +void dcbz_area(u32 start_address, u32 num_bytes); #endif /* __ASSEMBLY__ */ #endif /* _PPC4xx_SDRAM_H_ */ |