ppc4xx: CPU PPC440x5 on Virtex5 FX

-This patchs gives support for the embbedded ppc440
 on the Virtex5 FPGAs
-interrupts.c divided in uic.c and interrupts.c
-xilinx_irq.c for xilinx interrupt controller
-Include modifications propossed by  Stefan Roese

Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Acked-by: Stefan Roese <sr@denx.de>

4 files changed, 76 insertions, 0 deletions

diff --git a/include/asm-ppc/interrupt.h b/include/asm-ppc/interrupt.h
new file mode 100644
index 0000000..792836b
--- /dev/null
+++ b/include/asm-ppc/interrupt.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology  http://qtec.com/
+ * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+#ifndef INTERRUPT_H
+#define INTERRUPT_H
+
+#if defined(CONFIG_XILINX_440)
+#include <asm/xilinx_irq.h>
+#else
+#include <asm/ppc4xx-uic.h>
+#endif
+
+void pic_enable(void);
+void pic_irq_enable(unsigned int irq);
+void pic_irq_disable(unsigned int irq);
+void pic_irq_ack(unsigned int irq);
+void external_interrupt(struct pt_regs *regs);
+void interrupt_run_handler(int vec);
+
+#endif
diff --git a/include/asm-ppc/ppc4xx-uic.h b/include/asm-ppc/ppc4xx-uic.h
index d50c363..c908d42 100644
--- a/include/asm-ppc/ppc4xx-uic.h
+++ b/include/asm-ppc/ppc4xx-uic.h
@@ -43,6 +43,8 @@
 #define UIC_MAX		1
 #endif
 
+#define IRQ_MAX UIC_MAX * 32
+
 /*
  * UIC register
  */
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index b214844..dce4717 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -859,6 +859,8 @@
 #define PVR_86xx	0x80040000
 #define PVR_86xx_REV1	(PVR_86xx | 0x0010)
 
+#define PVR_VIRTEX5     0x7ff21912
+
 /*
  * For the 8xx processors, all of them report the same PVR family for
  * the PowerPC core. The various versions of these processors must be
diff --git a/include/asm-ppc/xilinx_irq.h b/include/asm-ppc/xilinx_irq.h
new file mode 100644
index 0000000..ddccc75
--- /dev/null
+++ b/include/asm-ppc/xilinx_irq.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology  http://qtec.com/
+ * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+#ifndef XILINX_IRQ_H
+#define XILINX_IRQ_H
+
+#define intc XPAR_INTC_0_BASEADDR
+#define ISR (intc+(0*4))	/* Interrupt Status Register */
+#define IPR (intc+(1*4))	/* Interrupt Pending Register */
+#define IER (intc+(2*4))	/* Interrupt Enable Register */
+#define IAR (intc+(3*4))	/* Interrupt Acknowledge Register */
+#define SIE (intc+(4*4))	/* Set Interrupt Enable bits */
+#define CIE (intc+(5*4))	/* Clear Interrupt Enable bits */
+#define IVR (intc+(6*4))	/* Interrupt Vector Register */
+#define MER (intc+(7*4))	/* Master Enable Register */
+
+#define IRQ_MASK(irq) (1<<(irq&0x1f))
+
+#define IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS
+
+#endif