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| author | Haiying Wang <Haiying.Wang@freescale.com> | 2008-10-03 12:36:39 -0400 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-10-18 21:54:04 +0200 |
| commit | dbbbb3abeff325855cae76e33d69d5665631443f (patch) | |
| tree | 2df59a7ac7364e4c501e228c74db3cd5f14ad3b1 /include/asm-ppc | |
| parent | 1c9aa76bf9013069e24258f46f4687c9f98a02d6 (diff) | |
| download | u-boot-imx-dbbbb3abeff325855cae76e33d69d5665631443f.zip u-boot-imx-dbbbb3abeff325855cae76e33d69d5665631443f.tar.gz u-boot-imx-dbbbb3abeff325855cae76e33d69d5665631443f.tar.bz2 | |
Make DDR interleaving mode work correctly
Fix some bugs:
1. Correctly set intlv_ctl in cs_config.
2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
3. Set base_address and total memory for each ddr controller in memory
controller interleaving mode.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Diffstat (limited to 'include/asm-ppc')
| -rw-r--r-- | include/asm-ppc/fsl_ddr_sdram.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h index 8adde34..c1ea7cd 100644 --- a/include/asm-ppc/fsl_ddr_sdram.h +++ b/include/asm-ppc/fsl_ddr_sdram.h @@ -36,6 +36,18 @@ typedef ddr2_spd_eeprom_t generic_spd_eeprom_t; typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #endif +/* define bank(chip select) interleaving mode */ +#define FSL_DDR_CS0_CS1 0x40 +#define FSL_DDR_CS2_CS3 0x20 +#define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3) +#define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04) + +/* define memory controller interleaving mode */ +#define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0 +#define FSL_DDR_PAGE_INTERLEAVING 0x1 +#define FSL_DDR_BANK_INTERLEAVING 0x2 +#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3 + /* Record of register values computed */ typedef struct fsl_ddr_cfg_regs_s { struct { |