Merge with git://www.denx.de/git/u-boot.git

7 files changed, 775 insertions, 29 deletions

diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h
index d1bb159..de82399 100644
--- a/include/asm-ppc/e300.h
+++ b/include/asm-ppc/e300.h
@@ -9,6 +9,7 @@
 #define PVR_E300C1	0x80830000
 #define PVR_E300C2	0x80840000
 #define PVR_E300C3	0x80850000
+#define PVR_E300C4	0x80860000
 
 /*
  * Hardware Implementation-Dependent Register 0 (HID0)
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index cd24636..bbaeb3f 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -85,6 +85,10 @@ typedef	struct	global_data {
 	unsigned long	ipb_clk;
 	unsigned long	pci_clk;
 #endif
+#if defined(CONFIG_MPC512X)
+	u32 ipb_clk;
+	u32 csb_clk;
+#endif /* CONFIG_MPC512X */
 #if defined(CONFIG_MPC8220)
 	unsigned long   bExtUart;
 	unsigned long   inp_clk;
diff --git a/include/asm-ppc/gpio.h b/include/asm-ppc/gpio.h
index 114dc92..c9b6a36 100644
--- a/include/asm-ppc/gpio.h
+++ b/include/asm-ppc/gpio.h
@@ -45,12 +45,14 @@ typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
 typedef enum gpio_out	 { GPIO_OUT_0, GPIO_OUT_1, GPIO_OUT_NO_CHG } gpio_out_t;
 
 typedef struct {
-	unsigned long add;	/* gpio core base address	*/
-	gpio_driver_t in_out;	/* Driver Setting		*/
-	gpio_select_t alt_nb;	/* Selected Alternate		*/
+	unsigned long	add;	/* gpio core base address	*/
+	gpio_driver_t	in_out;	/* Driver Setting		*/
+	gpio_select_t	alt_nb;	/* Selected Alternate		*/
+	gpio_out_t	out_val;/* Default Output Value		*/
 } gpio_param_s;
 #endif
 
 void gpio_config(int pin, int in_out, int gpio_alt, int out_val);
 void gpio_write_bit(int pin, int val);
+int gpio_read_out_bit(int pin);
 void gpio_set_chip_configuration(void);
diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h
new file mode 100644
index 0000000..23d10d4
--- /dev/null
+++ b/include/asm-ppc/immap_512x.h
@@ -0,0 +1,569 @@
+/*
+ * (C) Copyright 2007 DENX Software Engineering
+ *
+ * MPC512x Internal Memory Map
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Based on the MPC83xx header.
+ */
+
+#ifndef __IMMAP_512x__
+#define __IMMAP_512x__
+
+#include <asm/types.h>
+
+typedef struct law512x {
+	u32 bar;	/* Base Addr Register */
+	u32 ar;		/* Attributes Register */
+} law521x_t;
+
+/*
+ * System configuration registers
+ */
+typedef struct sysconf512x {
+	u32 immrbar;		/* Internal memory map base address register */
+	u8 res0[0x1c];
+	u32 lpbaw;		/* LP Boot Access Window */
+	u32 lpcs0aw;		/* LP CS0 Access Window */
+	u32 lpcs1aw;		/* LP CS1 Access Window */
+	u32 lpcs2aw;		/* LP CS2 Access Window */
+	u32 lpcs3aw;		/* LP CS3 Access Window */
+	u32 lpcs4aw;		/* LP CS4 Access Window */
+	u32 lpcs5aw;		/* LP CS5 Access Window */
+	u32 lpcs6aw;		/* LP CS6 Access Window */
+	u32 lpcs7aw;		/* LP CS7 Access Window */
+	u8 res1[0x1c];
+	law521x_t pcilaw[3];	/* PCI Local Access Window 0-2 Registers */
+	u8 res2[0x28];
+	law521x_t ddrlaw;	/* DDR Local Access Window */
+	u8 res3[0x18];
+	u32 mbxbar;		/* MBX Base Address */
+	u32 srambar;		/* SRAM Base Address */
+	u32 nfcbar;		/* NFC Base Address */
+	u8 res4[0x34];
+	u32 spridr;		/* System Part and Revision ID Register */
+	u32 spcr;		/* System Priority Configuration Register */
+	u8 res5[0xf8];
+} sysconf512x_t;
+
+/*
+ * Watch Dog Timer (WDT) Registers
+ */
+typedef struct wdt512x {
+	u8 res0[4];
+	u32 swcrr;		/* System watchdog control register */
+	u32 swcnr;		/* System watchdog count register */
+	u8 res1[2];
+	u16 swsrr;		/* System watchdog service register */
+	u8 res2[0xF0];
+} wdt512x_t;
+
+/*
+ * RTC Module Registers
+ */
+typedef struct rtclk512x {
+	u8 fixme[0x100];
+} rtclk512x_t;
+
+/*
+ * General Purpose Timer
+ */
+typedef struct gpt512x {
+	u8 fixme[0x100];
+} gpt512x_t;
+
+/*
+ * Integrated Programmable Interrupt Controller
+ */
+typedef struct ipic512x {
+	u8 fixme[0x100];
+} ipic512x_t;
+
+/*
+ * System Arbiter Registers
+ */
+typedef struct arbiter512x {
+	u32 acr;		/* Arbiter Configuration Register */
+	u32 atr;		/* Arbiter Timers Register */
+	u32 ater;		/* Arbiter Transfer Error Register */
+	u32 aer;		/* Arbiter Event Register */
+	u32 aidr;		/* Arbiter Interrupt Definition Register */
+	u32 amr;		/* Arbiter Mask Register */
+	u32 aeatr;		/* Arbiter Event Attributes Register */
+	u32 aeadr;		/* Arbiter Event Address Register */
+	u32 aerr;		/* Arbiter Event Response Register */
+	u8 res1[0xDC];
+} arbiter512x_t;
+
+/*
+ * Reset Module
+ */
+typedef struct reset512x {
+	u32 rcwl;		/* Reset Configuration Word Low Register */
+	u32 rcwh;		/* Reset Configuration Word High Register */
+	u8 res0[8];
+	u32 rsr;		/* Reset Status Register */
+	u32 rmr;		/* Reset Mode Register */
+	u32 rpr;		/* Reset protection Register */
+	u32 rcr;		/* Reset Control Register */
+	u32 rcer;		/* Reset Control Enable Register */
+	u8 res1[0xDC];
+} reset512x_t;
+
+/*
+ * Clock Module
+ */
+typedef struct clk512x {
+	u32 spmr;		/* System PLL Mode Register */
+	u32 sccr[2];		/* System Clock Control Registers */
+	u32 scfr[2];		/* System Clock Frequency Registers */
+	u8 res0[4];
+	u32 bcr;		/* Bread Crumb Register */
+	u32 pscccr[12];		/* PSC0-11 Clock Control Registers */
+	u32 spccr;		/* SPDIF Clock Control Registers */
+	u32 cccr;		/* CFM Clock Control Registers */
+	u32 dccr;		/* DIU Clock Control Registers */
+	u8 res1[0xa8];
+} clk512x_t;
+
+/*
+ * Power Management Control Module
+ */
+typedef struct pmc512x {
+	u8 fixme[0x100];
+} pmc512x_t;
+
+/*
+ * General purpose I/O module
+ */
+typedef struct gpio512x {
+	u8 fixme[0x100];
+} gpio512x_t;
+
+/*
+ * DDR Memory Controller Memory Map
+ */
+typedef struct ddr512x {
+	u32 ddr_sys_config;	/* System Configuration Register */
+	u32 ddr_time_config0;	/* Timing Configuration Register */
+	u32 ddr_time_config1;	/* Timing Configuration Register */
+	u32 ddr_time_config2;	/* Timing Configuration Register */
+	u32 ddr_command;	/* Command Register */
+	u32 ddr_compact_command;	/* Compact Command Register */
+	u32 self_refresh_cmd_0;	/* Enter/Exit Self Refresh Registers */
+	u32 self_refresh_cmd_1;	/* Enter/Exit Self Refresh Registers */
+	u32 self_refresh_cmd_2;	/* Enter/Exit Self Refresh Registers */
+	u32 self_refresh_cmd_3;	/* Enter/Exit Self Refresh Registers */
+	u32 self_refresh_cmd_4;	/* Enter/Exit Self Refresh Registers */
+	u32 self_refresh_cmd_5;	/* Enter/Exit Self Refresh Registers */
+	u32 self_refresh_cmd_6;	/* Enter/Exit Self Refresh Registers */
+	u32 self_refresh_cmd_7;	/* Enter/Exit Self Refresh Registers */
+	u32 DQS_config_offset_count;	/* DQS Config Offset Count */
+	u32 DQS_config_offset_time;	/* DQS Config Offset Time */
+	u32 DQS_delay_status;	/* DQS Delay Status */
+	u32 res0[0xF];
+	u32 prioman_config1;	/* Priority Manager Configuration */
+	u32 prioman_config2;	/* Priority Manager Configuration */
+	u32 hiprio_config;	/* High Priority Configuration */
+	u32 lut_table0_main_upper;	/* LUT0 Main Upper */
+	u32 lut_table1_main_upper;	/* LUT1 Main Upper */
+	u32 lut_table2_main_upper;	/* LUT2 Main Upper */
+	u32 lut_table3_main_upper;	/* LUT3 Main Upper */
+	u32 lut_table4_main_upper;	/* LUT4 Main Upper */
+	u32 lut_table0_main_lower;	/* LUT0 Main Lower */
+	u32 lut_table1_main_lower;	/* LUT1 Main Lower */
+	u32 lut_table2_main_lower;	/* LUT2 Main Lower */
+	u32 lut_table3_main_lower;	/* LUT3 Main Lower */
+	u32 lut_table4_main_lower;	/* LUT4 Main Lower */
+	u32 lut_table0_alternate_upper;	/* LUT0 Alternate Upper */
+	u32 lut_table1_alternate_upper; /* LUT1 Alternate Upper */
+	u32 lut_table2_alternate_upper; /* LUT2 Alternate Upper */
+	u32 lut_table3_alternate_upper; /* LUT3 Alternate Upper */
+	u32 lut_table4_alternate_upper; /* LUT4 Alternate Upper */
+	u32 lut_table0_alternate_lower; /* LUT0 Alternate Lower */
+	u32 lut_table1_alternate_lower; /* LUT1 Alternate Lower */
+	u32 lut_table2_alternate_lower; /* LUT2 Alternate Lower */
+	u32 lut_table3_alternate_lower; /* LUT3 Alternate Lower */
+	u32 lut_table4_alternate_lower; /* LUT4 Alternate Lower */
+	u32 performance_monitor_config;
+	u32 event_time_counter;
+	u32 event_time_preset;
+	u32 performance_monitor1_address_low;
+	u32 performance_monitor2_address_low;
+	u32 performance_monitor1_address_hi;
+	u32 performance_monitor2_address_hi;
+	u32 res1[2];
+	u32 performance_monitor1_read_counter;
+	u32 performance_monitor2_read_counter;
+	u32 performance_monitor1_write_counter;
+	u32 performance_monitor2_write_counter;
+	u32 granted_ack_counter0;
+	u32 granted_ack_counter1;
+	u32 granted_ack_counter2;
+	u32 granted_ack_counter3;
+	u32 granted_ack_counter4;
+	u32 cumulative_wait_counter0;
+	u32 cumulative_wait_counter1;
+	u32 cumulative_wait_counter2;
+	u32 cumulative_wait_counter3;
+	u32 cumulative_wait_counter4;
+	u32 summed_priority_counter0;
+	u32 summed_priority_counter1;
+	u32 summed_priority_counter2;
+	u32 summed_priority_counter3;
+	u32 summed_priority_counter4;
+	u32 res2[0x3AD];
+} ddr512x_t;
+
+
+/*
+ * DMA/Messaging Unit
+ */
+typedef struct dma512x {
+	u8 fixme[0x1800];
+} dma512x_t;
+
+/*
+ * PCI Software Configuration Registers
+ */
+typedef struct pciconf512x {
+	u8 fixme[0x80];
+} pciconf512x_t;
+
+/*
+ * Sequencer
+ */
+typedef struct ios512x {
+	u8 fixme[0x100];
+} ios512x_t;
+
+/*
+ * PCI Controller
+ */
+typedef struct pcictrl512x {
+	u8 fixme[0x100];
+} pcictrl512x_t;
+
+
+/*
+ * MSCAN
+ */
+typedef struct mscan512x {
+	u8 fixme[0x100];
+} mscan512x_t;
+
+/*
+ * BDLC
+ */
+typedef struct bdlc512x {
+	u8 fixme[0x100];
+} bdlc512x_t;
+
+/*
+ * SDHC
+ */
+typedef struct sdhc512x {
+	u8 fixme[0x100];
+} sdhc512x_t;
+
+/*
+ * SPDIF
+ */
+typedef struct spdif512x {
+	u8 fixme[0x100];
+} spdif512x_t;
+
+/*
+ * I2C
+ */
+typedef struct i2c512x_dev {
+	volatile u32 madr;		/* I2Cn + 0x00 */
+	volatile u32 mfdr;		/* I2Cn + 0x04 */
+	volatile u32 mcr;		/* I2Cn + 0x08 */
+	volatile u32 msr;		/* I2Cn + 0x0C */
+	volatile u32 mdr;		/* I2Cn + 0x10 */
+	u8 res0[0x0C];
+} i2c512x_dev_t;
+
+typedef struct i2c512x {
+	i2c512x_dev_t dev[3];
+	volatile u32 icr;
+	volatile u32 mifr;
+	u8 res0[0x98];
+} i2c512x_t;
+
+/*
+ * AXE
+ */
+typedef struct axe512x {
+	u8 fixme[0x100];
+} axe512x_t;
+
+/*
+ * DIU
+ */
+typedef struct diu512x {
+	u8 fixme[0x100];
+} diu512x_t;
+
+/*
+ * CFM
+ */
+typedef struct cfm512x {
+	u8 fixme[0x100];
+} cfm512x_t;
+
+/*
+ * FEC
+ */
+typedef struct fec512x {
+	u8 fixme[0x800];
+} fec512x_t;
+
+/*
+ * ULPI
+ */
+typedef struct ulpi512x {
+	u8 fixme[0x600];
+} ulpi512x_t;
+
+/*
+ * UTMI
+ */
+typedef struct utmi512x {
+	u8 fixme[0x3000];
+} utmi512x_t;
+
+/*
+ * PCI DMA
+ */
+typedef struct pcidma512x {
+	u8 fixme[0x300];
+} pcidma512x_t;
+
+/*
+ * IO Control
+ */
+typedef struct ioctrl512x {
+	u32 regs[0x400];
+} ioctrl512x_t;
+
+/*
+ * IIM
+ */
+typedef struct iim512x {
+	u8 fixme[0x1000];
+} iim512x_t;
+
+/*
+ * LPC
+ */
+typedef struct lpc512x {
+	u32	cs_cfg[8];	/* Chip Select N Configuration Registers
+				   No dedicated entry for CS Boot as == CS0 */
+	u32	cs_cr;		/* Chip Select Control Register */
+	u32	cs_sr;		/* Chip Select Status Register */
+	u32	cs_bcr;		/* Chip Select Burst Control Register */
+	u32	cs_dccr;	/* Chip Select Deadcycle Control Register */
+	u32	cs_hccr;	/* Chip Select Holdcycle Control Register */
+	u8	res0[0xcc];
+	u32	sclpc_psr;	/* SCLPC Packet Size Register */
+	u32	sclpc_sar;	/* SCLPC Start Address Register */
+	u32	sclpc_cr;	/* SCLPC Control Register */
+	u32	sclpc_er;	/* SCLPC Enable Register */
+	u32	sclpc_nar;	/* SCLPC NextAddress Register */
+	u32	sclpc_sr;	/* SCLPC Status Register */
+	u32	sclpc_bdr;	/* SCLPC Bytes Done Register */
+	u32	emb_scr;	/* EMB Share Counter Register */
+	u32	emb_pcr;	/* EMB Pause Control Register */
+	u8	res1[0x1c];
+	u32	lpc_fdwr;	/* LPC RX/TX FIFO Data Word Register */
+	u32	lpc_fsr;	/* LPC RX/TX FIFO Status Register */
+	u32	lpc_cr;		/* LPC RX/TX FIFO Control Register */
+	u32	lpc_ar;		/* LPC RX/TX FIFO Alarm Register */
+	u8	res2[0xb0];
+} lpc512x_t;
+
+/*
+ * PATA
+ */
+typedef struct pata512x {
+	u8 fixme[0x100];
+} pata512x_t;
+
+/*
+ * PSC
+ */
+typedef struct psc512x {
+	volatile u8	mode;		/* PSC + 0x00 */
+	volatile u8	res0[3];
+	union {				/* PSC + 0x04 */
+		volatile u16	status;
+		volatile u16	clock_select;
+	} sr_csr;
+#define psc_status	sr_csr.status
+#define psc_clock_select sr_csr.clock_select
+	volatile u16	res1;
+	volatile u8	command;	/* PSC + 0x08 */
+	volatile u8	res2[3];
+	union {				/* PSC + 0x0c */
+		volatile u8	buffer_8;
+		volatile u16	buffer_16;
+		volatile u32	buffer_32;
+	} buffer;
+#define psc_buffer_8	buffer.buffer_8
+#define psc_buffer_16	buffer.buffer_16
+#define psc_buffer_32	buffer.buffer_32
+	union {				/* PSC + 0x10 */
+		volatile u8	ipcr;
+		volatile u8	acr;
+	} ipcr_acr;
+#define psc_ipcr	ipcr_acr.ipcr
+#define psc_acr		ipcr_acr.acr
+	volatile u8	res3[3];
+	union {				/* PSC + 0x14 */
+		volatile u16	isr;
+		volatile u16	imr;
+	} isr_imr;
+#define psc_isr		isr_imr.isr
+#define psc_imr		isr_imr.imr
+	volatile u16	res4;
+	volatile u8	ctur;		/* PSC + 0x18 */
+	volatile u8	res5[3];
+	volatile u8	ctlr;		/* PSC + 0x1c */
+	volatile u8	res6[3];
+	volatile u32	ccr;		/* PSC + 0x20 */
+	volatile u8	res7[12];
+	volatile u8	ivr;		/* PSC + 0x30 */
+	volatile u8	res8[3];
+	volatile u8	ip;		/* PSC + 0x34 */
+	volatile u8	res9[3];
+	volatile u8	op1;		/* PSC + 0x38 */
+	volatile u8	res10[3];
+	volatile u8	op0;		/* PSC + 0x3c */
+	volatile u8	res11[3];
+	volatile u32	sicr;		/* PSC + 0x40 */
+	volatile u8	res12[60];
+	volatile u32	tfcmd;		/* PSC + 0x80 */
+	volatile u32	tfalarm;	/* PSC + 0x84 */
+	volatile u32	tfstat;		/* PSC + 0x88 */
+	volatile u32	tfintstat;	/* PSC + 0x8C */
+	volatile u32	tfintmask;	/* PSC + 0x90 */
+	volatile u32	tfcount;	/* PSC + 0x94 */
+	volatile u16	tfwptr;		/* PSC + 0x98 */
+	volatile u16	tfrptr;		/* PSC + 0x9A */
+	volatile u32	tfsize;		/* PSC + 0x9C */
+	volatile u8	res13[28];
+	union {				/* PSC + 0xBC */
+		volatile u8	buffer_8;
+		volatile u16	buffer_16;
+		volatile u32	buffer_32;
+	} tfdata_buffer;
+#define tfdata_8	tfdata_buffer.buffer_8
+#define tfdata_16	tfdata_buffer.buffer_16
+#define tfdata_32	tfdata_buffer.buffer_32
+
+	volatile u32	rfcmd;		/* PSC + 0xC0 */
+	volatile u32	rfalarm;	/* PSC + 0xC4 */
+	volatile u32	rfstat;		/* PSC + 0xC8 */
+	volatile u32	rfintstat;	/* PSC + 0xCC */
+	volatile u32	rfintmask;	/* PSC + 0xD0 */
+	volatile u32	rfcount;	/* PSC + 0xD4 */
+	volatile u16	rfwptr;		/* PSC + 0xD8 */
+	volatile u16	rfrptr;		/* PSC + 0xDA */
+	volatile u32	rfsize;		/* PSC + 0xDC */
+	volatile u8	res18[28];
+	union {				/* PSC + 0xFC */
+		volatile u8	buffer_8;
+		volatile u16	buffer_16;
+		volatile u32	buffer_32;
+	} rfdata_buffer;
+#define rfdata_8	rfdata_buffer.buffer_8
+#define rfdata_16	rfdata_buffer.buffer_16
+#define rfdata_32	rfdata_buffer.buffer_32
+} psc512x_t;
+
+/*
+ * FIFOC
+ */
+typedef struct fifoc512x {
+	u32 fifoc_cmd;
+	u32 fifoc_int;
+	u32 fifoc_dma;
+	u32 fifoc_axe;
+	u32 fifoc_debug;
+	u8 fixme[0xEC];
+} fifoc512x_t;
+
+/*
+ * SATA
+ */
+typedef struct sata512x {
+	u8 fixme[0x2000];
+} sata512x_t;
+
+typedef struct immap {
+	sysconf512x_t		sysconf;	/* System configuration */
+	u8			res0[0x700];
+	wdt512x_t		wdt;		/* Watch Dog Timer (WDT) */
+	rtclk512x_t		rtc;		/* Real Time Clock Module */
+	gpt512x_t		gpt;		/* General Purpose Timer */
+	ipic512x_t		ipic;		/* Integrated Programmable Interrupt Controller */
+	arbiter512x_t		arbiter;	/* CSB Arbiter */
+	reset512x_t		reset;		/* Reset Module */
+	clk512x_t		clk;		/* Clock Module */
+	pmc512x_t		pmc;		/* Power Management Control Module */
+	gpio512x_t		gpio;		/* General purpose I/O module */
+	u8			res1[0x100];
+	mscan512x_t		mscan;		/* MSCAN */
+	bdlc512x_t		bdlc;		/* BDLC */
+	sdhc512x_t		sdhc;		/* SDHC */
+	spdif512x_t		spdif;		/* SPDIF */
+	i2c512x_t		i2c;		/* I2C Controllers */
+	u8			res2[0x800];
+	axe512x_t		axe;		/* AXE */
+	diu512x_t		diu;		/* Display Interface Unit */
+	cfm512x_t		cfm;		/* Clock Frequency Measurement */
+	u8			res3[0x500];
+	fec512x_t		fec;		/* Fast Ethernet Controller */
+	ulpi512x_t		ulpi;		/* USB ULPI */
+	u8			res4[0xa00];
+	utmi512x_t		utmi;		/* USB UTMI */
+	u8			res5[0x1000];
+	pcidma512x_t		pci_dma;	/* PCI DMA */
+	pciconf512x_t		pci_conf;	/* PCI Configuration */
+	u8			res6[0x80];
+	ios512x_t		ios;		/* PCI Sequencer */
+	pcictrl512x_t		pci_ctrl;	/* PCI Controller Control and Status */
+	u8			res7[0xa00];
+	ddr512x_t		mddrc;		/* Multi-port DDR Memory Controller */
+	ioctrl512x_t		io_ctrl;	/* IO Control */
+	iim512x_t		iim;		/* IC Identification module */
+	u8			res8[0x4000];
+	lpc512x_t		lpc;		/* LocalPlus Controller */
+	pata512x_t		pata;		/* Parallel ATA */
+	u8			res9[0xd00];
+	psc512x_t		psc[12];	/* PSCs */
+	u8			res10[0x300];
+	fifoc512x_t		fifoc;		/* FIFO Controller */
+	u8			res11[0x2000];
+	dma512x_t		dma;		/* DMA */
+	u8			res12[0xa800];
+	sata512x_t		sata;		/* Serial ATA */
+	u8			res13[0xde000];
+} immap_t;
+#endif /* __IMMAP_512x__ */
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 5377c2e..e002d28 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1548,7 +1548,9 @@ typedef struct ccsr_gur {
 	char	res9[12];
 	uint	pvr;		/* 0xe00a0 - Processor version register */
 	uint	svr;		/* 0xe00a4 - System version register */
-	char	res10[3416];
+	char	res10a[8];
+	uint	rstcr;		/* 0xe00b0 - Reset control register */
+	char	res10b[3404];
 	uint	clkocr;		/* 0xe0e00 - Clock out select register */
 	char	res11[12];
 	uint	ddrdllcr;	/* 0xe0e10 - DDR DLL control register */
diff --git a/include/asm-ppc/immap_fsl_pci.h b/include/asm-ppc/immap_fsl_pci.h
new file mode 100644
index 0000000..bd732b6
--- /dev/null
+++ b/include/asm-ppc/immap_fsl_pci.h
@@ -0,0 +1,150 @@
+/* (C) Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __IMMAP_85xx_fsl_pci__
+#define __IMMAP_85xx_fsl_pci__
+
+/*
+ * Common PCI/PCIE Register structure for mpc85xx and mpc86xx
+ */
+
+/*
+ * PCI Translation Registers
+ */
+typedef struct pci_outbound_window {
+	u32	potar;		/* 0x00 - Address */
+	u32	potear;		/* 0x04 - Address Extended */
+	u32	powbar;		/* 0x08 - Window Base Address */
+	u32	res1;
+	u32	powar;		/* 0x10 - Window Attributes */
+#define POWAR_EN	0x80000000
+#define POWAR_IO_READ	0x00080000
+#define POWAR_MEM_READ	0x00040000
+#define POWAR_IO_WRITE	0x00008000
+#define POWAR_MEM_WRITE	0x00004000
+	u32	res2[3];
+} pot_t;
+
+typedef struct pci_inbound_window {
+	u32	pitar;		/* 0x00 - Address */
+	u32	res1;
+	u32	piwbar;		/* 0x08 - Window Base Address */
+	u32	piwbear;	/* 0x0c - Window Base Address Extended */
+	u32	piwar;		/* 0x10 - Window Attributes */
+#define PIWAR_EN		0x80000000
+#define PIWAR_PF		0x20000000
+#define PIWAR_LOCAL		0x00f00000
+#define PIWAR_READ_SNOOP	0x00050000
+#define PIWAR_WRITE_SNOOP	0x00005000
+	u32	res2[3];
+} pit_t;
+
+/* PCI/PCI Express Registers */
+typedef struct ccsr_pci {
+	u32	cfg_addr;	/* 0x000 - PCI Configuration Address Register */
+	u32	cfg_data;	/* 0x004 - PCI Configuration Data Register */
+	u32	int_ack;	/* 0x008 - PCI Interrupt Acknowledge Register */
+	u32	out_comp_to;	/* 0x00C - PCI Outbound Completion Timeout Register */
+	u32	out_conf_to;	/* 0x010 - PCI Configuration Timeout Register */
+	u32	config;		/* 0x014 - PCIE CONFIG Register */
+	char	res2[8];
+	u32	pme_msg_det;	/* 0x020 - PCIE PME & message detect register */
+	u32	pme_msg_dis;	/* 0x024 - PCIE PME & message disable register */
+	u32	pme_msg_int_en;	/* 0x028 - PCIE PME & message interrupt enable register */
+	u32	pm_command;	/* 0x02c - PCIE PM Command register */
+	char	res4[3016];	/*     (- #xbf8	 #x30)3016 */
+	u32	block_rev1;	/* 0xbf8 - PCIE Block Revision register 1 */
+	u32	block_rev2;	/* 0xbfc - PCIE Block Revision register 2 */
+
+	pot_t	pot[5];		/* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */
+	u32	res5[64];
+	pit_t	pit[3];		/* 0xda0 - 0xdff Inbound ATMU's 3, 2, and 1 */
+#define PIT3 0
+#define PIT2 1
+#define PIT1 2
+
+#if 0
+	u32	potar0;		/* 0xc00 - PCI Outbound Transaction Address Register 0 */
+	u32	potear0;	/* 0xc04 - PCI Outbound Translation Extended Address Register 0 */
+	char	res5[8];
+	u32	powar0;		/* 0xc10 - PCI Outbound Window Attributes Register 0 */
+	char	res6[12];
+	u32	potar1;		/* 0xc20 - PCI Outbound Transaction Address Register 1 */
+	u32	potear1;	/* 0xc24 - PCI Outbound Translation Extended Address Register 1 */
+	u32	powbar1;	/* 0xc28 - PCI Outbound Window Base Address Register 1 */
+	char	res7[4];
+	u32	powar1;		/* 0xc30 - PCI Outbound Window Attributes Register 1 */
+	char	res8[12];
+	u32	potar2;		/* 0xc40 - PCI Outbound Transaction Address Register 2 */
+	u32	potear2;	/* 0xc44 - PCI Outbound Translation Extended Address Register 2 */
+	u32	powbar2;	/* 0xc48 - PCI Outbound Window Base Address Register 2 */
+	char	res9[4];
+	u32	powar2;		/* 0xc50 - PCI Outbound Window Attributes Register 2 */
+	char	res10[12];
+	u32	potar3;		/* 0xc60 - PCI Outbound Transaction Address Register 3 */
+	u32	potear3;	/* 0xc64 - PCI Outbound Translation Extended Address Register 3 */
+	u32	powbar3;	/* 0xc68 - PCI Outbound Window Base Address Register 3 */
+	char	res11[4];
+	u32	powar3;		/* 0xc70 - PCI Outbound Window Attributes Register 3 */
+	char	res12[12];
+	u32	potar4;		/* 0xc80 - PCI Outbound Transaction Address Register 4 */
+	u32	potear4;	/* 0xc84 - PCI Outbound Translation Extended Address Register 4 */
+	u32	powbar4;	/* 0xc88 - PCI Outbound Window Base Address Register 4 */
+	char	res13[4];
+	u32	powar4;		/* 0xc90 - PCI Outbound Window Attributes Register 4 */
+	char	res14[268];
+	u32	pitar3;		/* 0xda0 - PCI Inbound Translation Address Register 3 */
+	char	res15[4];
+	u32	piwbar3;	/* 0xda8 - PCI Inbound Window Base Address Register 3 */
+	u32	piwbear3;	/* 0xdac - PCI Inbound Window Base Extended Address Register 3 */
+	u32	piwar3;		/* 0xdb0 - PCI Inbound Window Attributes Register 3 */
+	char	res16[12];
+	u32	pitar2;		/* 0xdc0 - PCI Inbound Translation Address Register 2 */
+	char	res17[4];
+	u32	piwbar2;	/* 0xdc8 - PCI Inbound Window Base Address Register 2 */
+	u32	piwbear2;	/* 0xdcc - PCI Inbound Window Base Extended Address Register 2 */
+	u32	piwar2;		/* 0xdd0 - PCI Inbound Window Attributes Register 2 */
+	char	res18[12];
+	u32	pitar1;		/* 0xde0 - PCI Inbound Translation Address Register 1 */
+	char	res19[4];
+	u32	piwbar1;	/* 0xde8 - PCI Inbound Window Base Address Register 1 */
+	char	res20[4];
+	u32	piwar1;		/* 0xdf0 - PCI Inbound Window Attributes Register 1 */
+	char	res21[12];
+#endif
+	u32	pedr;		/* 0xe00 - PCI Error Detect Register */
+	u32	pecdr;		/* 0xe04 - PCI Error Capture Disable Register */
+	u32	peer;		/* 0xe08 - PCI Error Interrupt Enable Register */
+	u32	peattrcr;	/* 0xe0c - PCI Error Attributes Capture Register */
+	u32	peaddrcr;	/* 0xe10 - PCI Error Address Capture Register */
+/*	u32	perr_disr	 * 0xe10 - PCIE Erorr Disable Register */
+	u32	peextaddrcr;	/* 0xe14 - PCI	Error Extended Address Capture Register */
+	u32	pedlcr;		/* 0xe18 - PCI Error Data Low Capture Register */
+	u32	pedhcr;		/* 0xe1c - PCI Error Error Data High Capture Register */
+	u32	gas_timr;	/* 0xe20 - PCI Gasket Timer Register */
+/*	u32	perr_cap_stat;	 * 0xe20 - PCIE Error Capture Status Register */
+	char	res22[4];
+	u32	perr_cap0;	/* 0xe28 - PCIE Error Capture Register 0 */
+	u32	perr_cap1;	/* 0xe2c - PCIE Error Capture Register 1 */
+	u32	perr_cap2;	/* 0xe30 - PCIE Error Capture Register 2 */
+	u32	perr_cap3;	/* 0xe34 - PCIE Error Capture Register 3 */
+	char	res23[456];	/*     (- #x1000 #xe38) 456 */
+} ccsr_fsl_pci_t;
+
+#endif /*__IMMAP_fsl_pci__*/
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 5efc3ee..71e2e84 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -35,18 +35,18 @@
 #define MSR_DWE         (1<<10)         /* Debug Wait Enable (4xx) */
 #define MSR_UBLE        (1<<10)         /* BTB lock enable (e500) */
 #define MSR_BE		(1<<9)		/* Branch Trace */
-#define MSR_DE		(1<<9) 		/* Debug Exception Enable */
+#define MSR_DE		(1<<9)		/* Debug Exception Enable */
 #define MSR_FE1		(1<<8)		/* Floating Exception mode 1 */
 #define MSR_IP		(1<<6)		/* Exception prefix 0x000/0xFFF */
-#define MSR_IR		(1<<5) 		/* Instruction Relocate */
+#define MSR_IR		(1<<5)		/* Instruction Relocate */
 #define MSR_IS          (1<<5)          /* Book E Instruction space */
-#define MSR_DR		(1<<4) 		/* Data Relocate */
+#define MSR_DR		(1<<4)		/* Data Relocate */
 #define MSR_DS          (1<<4)          /* Book E Data space */
 #define MSR_PE		(1<<3)		/* Protection Enable */
 #define MSR_PX		(1<<2)		/* Protection Exclusive Mode */
 #define MSR_PMM         (1<<2)          /* Performance monitor mark bit (e500) */
 #define MSR_RI		(1<<1)		/* Recoverable Exception */
-#define MSR_LE		(1<<0) 		/* Little Endian */
+#define MSR_LE		(1<<0)		/* Little Endian */
 
 #ifdef CONFIG_APUS_FAST_EXCEPT
 #define MSR_		MSR_ME|MSR_IP|MSR_RI
@@ -58,7 +58,6 @@
 #else
 #define MSR_KERNEL	MSR_ME
 #endif
-#define MSR_USER	MSR_KERNEL|MSR_PR|MSR_EE
 
 /* Floating Point Status and Control Register (FPSCR) Fields */
 
@@ -123,9 +122,9 @@
 #define   DBCR_EDM	0x80000000
 #define   DBCR_IDM	0x40000000
 #define   DBCR_RST(x)	(((x) & 0x3) << 28)
-#define     DBCR_RST_NONE       	0
-#define     DBCR_RST_CORE       	1
-#define     DBCR_RST_CHIP       	2
+#define     DBCR_RST_NONE		0
+#define     DBCR_RST_CORE		1
+#define     DBCR_RST_CHIP		2
 #define     DBCR_RST_SYSTEM		3
 #define   DBCR_IC	0x08000000	/* Instruction Completion Debug Evnt */
 #define   DBCR_BT	0x04000000	/* Branch Taken Debug Event */
@@ -266,7 +265,7 @@
 #define SPRN_ICMP	0x3D5	/* Instruction TLB Compare Register */
 #define SPRN_ICTC	0x3FB	/* Instruction Cache Throttling Control Reg */
 #define SPRN_IMISS	0x3D4	/* Instruction TLB Miss Register */
-#define SPRN_IMMR	0x27E  	/* Internal Memory Map Register */
+#define SPRN_IMMR	0x27E	/* Internal Memory Map Register */
 #define SPRN_LDSTCR	0x3F8   /* Load/Store Control Register */
 #define SPRN_L2CR	0x3F9	/* Level 2 Cache Control Regsiter */
 #define SPRN_LR		0x008	/* Link Register */
@@ -308,7 +307,7 @@
 #define SPRN_SRR0	0x01A	/* Save/Restore Register 0 */
 #define SPRN_SRR1	0x01B	/* Save/Restore Register 1 */
 #define SPRN_SRR2	0x3DE	/* Save/Restore Register 2 */
-#define SPRN_SRR3 	0x3DF	/* Save/Restore Register 3 */
+#define SPRN_SRR3	0x3DF	/* Save/Restore Register 3 */
 #ifdef CONFIG_BOOKE
 #define SPRN_SVR	0x3FF	/* System Version Register */
 #else
@@ -451,6 +450,17 @@
 #define SPRN_PID1       0x279   /* Process ID Register 1 */
 #define SPRN_PID2       0x27a   /* Process ID Register 2 */
 #define SPRN_MCSR	0x23c	/* Machine Check Syndrome register */
+#ifdef CONFIG_440
+#define MCSR_MCS	0x80000000	/* Machine Check Summary */
+#define MCSR_IB		0x40000000	/* Instruction PLB Error */
+#define MCSR_DRB	0x20000000	/* Data Read PLB Error */
+#define MCSR_DWB	0x10000000	/* Data Write PLB Error */
+#define MCSR_TLBP	0x08000000	/* TLB Parity Error */
+#define MCSR_ICP	0x04000000	/* I-Cache Parity Error */
+#define MCSR_DCSP	0x02000000	/* D-Cache Search Parity Error */
+#define MCSR_DCFP	0x01000000	/* D-Cache Flush Parity Error */
+#define MCSR_IMPE	0x00800000	/* Imprecise Machine Check Exception */
+#endif
 #define ESR_ST          0x00800000      /* Store Operation */
 
 #if defined(CONFIG_MPC86xx)
@@ -484,17 +494,17 @@
 #define DBCR0	SPRN_DBCR0	/* Debug Control Register 0 */
 #define DBCR1	SPRN_DBCR1	/* Debug Control Register 1 */
 #define DBSR	SPRN_DBSR	/* Debug Status Register */
-#define DCMP	SPRN_DCMP      	/* Data TLB Compare Register */
-#define DEC	SPRN_DEC       	/* Decrement Register */
-#define DMISS	SPRN_DMISS     	/* Data TLB Miss Register */
+#define DCMP	SPRN_DCMP	/* Data TLB Compare Register */
+#define DEC	SPRN_DEC	/* Decrement Register */
+#define DMISS	SPRN_DMISS	/* Data TLB Miss Register */
 #define DSISR	SPRN_DSISR	/* Data Storage Interrupt Status Register */
-#define EAR	SPRN_EAR       	/* External Address Register */
+#define EAR	SPRN_EAR	/* External Address Register */
 #define ESR	SPRN_ESR	/* Exception Syndrome Register */
 #define HASH1	SPRN_HASH1	/* Primary Hash Address Register */
 #define HASH2	SPRN_HASH2	/* Secondary Hash Address Register */
 #define HID0	SPRN_HID0	/* Hardware Implementation Register 0 */
 #define HID1	SPRN_HID1	/* Hardware Implementation Register 1 */
-#define IABR	SPRN_IABR      	/* Instruction Address Breakpoint Register */
+#define IABR	SPRN_IABR	/* Instruction Address Breakpoint Register */
 #define IAC1	SPRN_IAC1	/* Instruction Address Register 1 */
 #define IAC2	SPRN_IAC2	/* Instruction Address Register 2 */
 #define IBAT0L	SPRN_IBAT0L	/* Instruction BAT 0 Lower Register */
@@ -511,13 +521,13 @@
 #define IBAT5U	SPRN_IBAT5U	/* Instruction BAT 5 Upper Register */
 #define IBAT6L	SPRN_IBAT6L	/* Instruction BAT 6 Lower Register */
 #define IBAT6U	SPRN_IBAT6U	/* Instruction BAT 6 Upper Register */
-#define IBAT7L 	SPRN_IBAT7L	/* Instruction BAT 7 Lower Register */
+#define IBAT7L	SPRN_IBAT7L	/* Instruction BAT 7 Lower Register */
 #define IBAT7U	SPRN_IBAT7U	/* Instruction BAT 7 Lower Register */
 #define ICMP	SPRN_ICMP	/* Instruction TLB Compare Register */
 #define IMISS	SPRN_IMISS	/* Instruction TLB Miss Register */
-#define IMMR	SPRN_IMMR      	/* PPC 860/821 Internal Memory Map Register */
+#define IMMR	SPRN_IMMR	/* PPC 860/821 Internal Memory Map Register */
 #define LDSTCR	SPRN_LDSTCR     /* Load/Store Control Register */
-#define L2CR	SPRN_L2CR    	/* PPC 750 L2 control register */
+#define L2CR	SPRN_L2CR	/* PPC 750 L2 control register */
 #define LR	SPRN_LR
 #define MBAR    SPRN_MBAR       /* System memory base address */
 #if defined(CONFIG_MPC86xx)
@@ -529,7 +539,7 @@
 #define SVR	SPRN_SVR	/* System-On-Chip Version Register */
 #define PVR	SPRN_PVR	/* Processor Version */
 #define RPA	SPRN_RPA	/* Required Physical Address Register */
-#define SDR1	SPRN_SDR1      	/* MMU hash base register */
+#define SDR1	SPRN_SDR1	/* MMU hash base register */
 #define SPR0	SPRN_SPRG0	/* Supervisor Private Registers */
 #define SPR1	SPRN_SPRG1
 #define SPR2	SPRN_SPRG2
@@ -544,6 +554,8 @@
 #define SPRG7   SPRN_SPRG7
 #define SRR0	SPRN_SRR0	/* Save and Restore Register 0 */
 #define SRR1	SPRN_SRR1	/* Save and Restore Register 1 */
+#define SRR2	SPRN_SRR2	/* Save and Restore Register 2 */
+#define SRR3	SPRN_SRR3	/* Save and Restore Register 3 */
 #define SVR	SPRN_SVR	/* System Version Register */
 #define TBRL	SPRN_TBRL	/* Time Base Read Lower Register */
 #define TBRU	SPRN_TBRU	/* Time Base Read Upper Register */
@@ -598,7 +610,7 @@
 #define IVOR35	SPRN_IVOR35
 #define MCSRR0	SPRN_MCSRR0
 #define MCSRR1	SPRN_MCSRR1
-#define L1CSR0 	SPRN_L1CSR0
+#define L1CSR0	SPRN_L1CSR0
 #define L1CSR1	SPRN_L1CSR1
 #define MCSR	SPRN_MCSR
 #define MMUCSR0	SPRN_MMUCSR0
@@ -607,7 +619,7 @@
 #define PID1	SPRN_PID1
 #define PID2	SPRN_PID2
 #define MAS0	SPRN_MAS0
-#define MAS1 	SPRN_MAS1
+#define MAS1	SPRN_MAS1
 #define MAS2	SPRN_MAS2
 #define MAS3	SPRN_MAS3
 #define MAS4	SPRN_MAS4
@@ -615,11 +627,17 @@
 #define MAS6	SPRN_MAS6
 #define MAS7	SPRN_MAS7
 
+#if defined(CONFIG_4xx) || defined(CONFIG_44x) || defined(CONFIG_MPC85xx)
+#define DAR_DEAR DEAR
+#else
+#define DAR_DEAR DAR
+#endif
+
 /* Device Control Registers */
 
 #define DCRN_BEAR	0x090	/* Bus Error Address Register */
 #define DCRN_BESR	0x091	/* Bus Error Syndrome Register */
-#define   BESR_DSES    	0x80000000	/* Data-Side Error Status */
+#define   BESR_DSES	0x80000000	/* Data-Side Error Status */
 #define   BESR_DMES	0x40000000	/* DMA Error Status */
 #define   BESR_RWS	0x20000000	/* Read/Write Status */
 #define   BESR_ETMASK	0x1C000000	/* Error Type */
@@ -676,8 +694,8 @@
 #define   IOCR_E3LP	0x01000000
 #define   IOCR_E4TE	0x00800000
 #define   IOCR_E4LP	0x00400000
-#define   IOCR_EDT     	0x00080000
-#define   IOCR_SOR     	0x00040000
+#define   IOCR_EDT	0x00080000
+#define   IOCR_SOR	0x00040000
 #define   IOCR_EDO	0x00008000
 #define   IOCR_2XC	0x00004000
 #define   IOCR_ATC	0x00002000
@@ -802,7 +820,7 @@
 #define PVR_823		PVR_821
 #define PVR_850		PVR_821
 #define PVR_860		PVR_821
-#define PVR_7400       	0x000C0000
+#define PVR_7400	0x000C0000
 #define PVR_8240	0x00810100
 
 /*