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authorTimur Tabi <timur@freescale.com>2008-01-07 13:31:19 -0600
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2008-01-09 16:28:12 -0600
commitb8ec2385038c094b07ec5b49336289a46b6e9cc6 (patch)
treececfa15b2de1ed5be9716c81df2da7a2a4b34b63 /include/asm-ppc
parentb009f3eca99bb7b9e6ba6639a8909a138dd5e9fe (diff)
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85xx: add ability to upload QE firmware
Define the layout of a binary blob that contains a QE firmware and instructions on how to upload it. Add function qe_upload_firmware() to parse the blob and perform the actual upload. Add command-line command "qe fw" to take a firmware blob in memory and upload it. Update ft_cpu_setup() on 85xx to create the 'firmware' device tree node if U-Boot has uploaded a firmware. Fully define 'struct rsp' in immap_qe.h to include the actual RISC Special Registers. Signed-off-by: Timur Tabi <timur@freescale.com>
Diffstat (limited to 'include/asm-ppc')
-rw-r--r--include/asm-ppc/immap_qe.h33
1 files changed, 31 insertions, 2 deletions
diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h
index a16a6d3..39da377 100644
--- a/include/asm-ppc/immap_qe.h
+++ b/include/asm-ppc/immap_qe.h
@@ -513,10 +513,39 @@ typedef struct dbg {
u8 res2[0x48];
} __attribute__ ((packed)) dbg_t;
-/* RISC Special Registers (Trap and Breakpoint)
+/*
+ * RISC Special Registers (Trap and Breakpoint). These are described in
+ * the QE Developer's Handbook.
*/
typedef struct rsp {
- u8 fixme[0x100];
+ u32 tibcr[16]; /* Trap/instruction breakpoint control regs */
+ u8 res0[64];
+ u32 ibcr0;
+ u32 ibs0;
+ u32 ibcnr0;
+ u8 res1[4];
+ u32 ibcr1;
+ u32 ibs1;
+ u32 ibcnr1;
+ u32 npcr;
+ u32 dbcr;
+ u32 dbar;
+ u32 dbamr;
+ u32 dbsr;
+ u32 dbcnr;
+ u8 res2[12];
+ u32 dbdr_h;
+ u32 dbdr_l;
+ u32 dbdmr_h;
+ u32 dbdmr_l;
+ u32 bsr;
+ u32 bor;
+ u32 bior;
+ u8 res3[4];
+ u32 iatr[4];
+ u32 eccr; /* Exception control configuration register */
+ u32 eicr;
+ u8 res4[0x100-0xf8];
} __attribute__ ((packed)) rsp_t;
typedef struct qe_immap {