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authorStefan Roese <sr@denx.de>2007-10-18 07:39:38 +0200
committerStefan Roese <sr@denx.de>2007-10-31 21:20:50 +0100
commit5cb4af4791f61843432155142b6cfac901f66c10 (patch)
tree1d8d742205d91220a21da7b2df45543163354253 /include/asm-ppc
parentd4cb2d17946466740afeb195a57d6cb290bf4cc0 (diff)
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ppc4xx: Add PCIe endpoint support on Kilauea (405EX)
This patch adds endpoint support for the AMCC Kilauea eval board. It can be tested by connecting a reworked PCIe cable (only 1x lane singles connected) to another root-complex. In this test setup, a 64MB inbound window is configured at BAR0 which maps to 0 on the PLB side. So accessing this BAR0 from the root-complex will access the first 64MB of the SDRAM on the PPC side. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/asm-ppc')
-rw-r--r--include/asm-ppc/4xx_pcie.h11
1 files changed, 8 insertions, 3 deletions
diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h
index 1830c6a..ffe0770 100644
--- a/include/asm-ppc/4xx_pcie.h
+++ b/include/asm-ppc/4xx_pcie.h
@@ -218,7 +218,8 @@
#define PECFG_BAR0LMPA 0x210
#define PECFG_BAR0HMPA 0x214
#define PECFG_BAR1MPA 0x218
-#define PECFG_BAR2MPA 0x220
+#define PECFG_BAR2LMPA 0x220
+#define PECFG_BAR2HMPA 0x224
#define PECFG_PIMEN 0x33c
#define PECFG_PIM0LAL 0x340
@@ -259,9 +260,13 @@ int pcie_hose_scan(struct pci_controller *hose, int bus);
*/
static inline int is_end_point(int port)
{
- static char s[10], *tk;
+ char s[10], *tk;
+ char *pcie_mode = getenv("pcie_mode");
- strcpy(s, getenv("pcie_mode"));
+ if (pcie_mode == NULL)
+ return 0;
+
+ strcpy(s, pcie_mode);
tk = strtok(s, ":");
switch (port) {