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authorMarian Balakowicz <m8@semihalf.com>2006-06-30 18:19:42 +0200
committerMarian Balakowicz <m8@semihalf.com>2006-06-30 18:19:42 +0200
commitf6e5739a68131998a5ae8aa0cf56a0316f810200 (patch)
tree010b89799af2478323c7f1cc04665b51b5cc4e50 /include/asm-ppc
parentf73e73ba0e422e6f79030d77286dd57becaee16f (diff)
parent6c5879f380be38d85fef0d3aba3353358f4b2ff4 (diff)
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Merge: Add support for AMCC 440SPe CPU based eval board (Yucca).
Diffstat (limited to 'include/asm-ppc')
-rw-r--r--include/asm-ppc/mmu.h41
-rw-r--r--include/asm-ppc/processor.h2
2 files changed, 43 insertions, 0 deletions
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index 2606b79..baaf6f7 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -470,4 +470,45 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
#define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19)
#define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20)
+#ifdef CONFIG_440SPE
+/*----------------------------------------------------------------------------+
+| Following instructions are not available in Book E mode of the GNU assembler.
++----------------------------------------------------------------------------*/
+#define DCCCI(ra,rb) .long 0x7c000000|\
+ (ra<<16)|(rb<<11)|(454<<1)
+
+#define ICCCI(ra,rb) .long 0x7c000000|\
+ (ra<<16)|(rb<<11)|(966<<1)
+
+#define DCREAD(rt,ra,rb) .long 0x7c000000|\
+ (rt<<21)|(ra<<16)|(rb<<11)|(486<<1)
+
+#define ICREAD(ra,rb) .long 0x7c000000|\
+ (ra<<16)|(rb<<11)|(998<<1)
+
+#define TLBSX(rt,ra,rb) .long 0x7c000000|\
+ (rt<<21)|(ra<<16)|(rb<<11)|(914<<1)
+
+#define TLBWE(rs,ra,ws) .long 0x7c000000|\
+ (rs<<21)|(ra<<16)|(ws<<11)|(978<<1)
+
+#define TLBRE(rt,ra,ws) .long 0x7c000000|\
+ (rt<<21)|(ra<<16)|(ws<<11)|(946<<1)
+
+#define TLBSXDOT(rt,ra,rb) .long 0x7c000001|\
+ (rt<<21)|(ra<<16)|(rb<<11)|(914<<1)
+
+#define MSYNC .long 0x7c000000|\
+ (598<<1)
+
+#define MBAR_INST .long 0x7c000000|\
+ (854<<1)
+
+/*----------------------------------------------------------------------------+
+| Following instruction is not available in PPC405 mode of the GNU assembler.
++----------------------------------------------------------------------------*/
+#define TLBRE(rt,ra,ws) .long 0x7c000000|\
+ (rt<<21)|(ra<<16)|(ws<<11)|(946<<1)
+
+#endif
#endif /* _PPC_MMU_H_ */
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 9ff03af..ea5b0d2 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -735,6 +735,8 @@
#define PVR_405EP_RB 0x51210950
#define PVR_440SP_RA 0x53221850
#define PVR_440SP_RB 0x53221891
+#define PVR_440SPe_RA 0x53421890
+#define PVR_440SPe_RB 0x53521891
#define PVR_601 0x00010000
#define PVR_602 0x00050000
#define PVR_603 0x00030000