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authorTimur Tabi <timur@freescale.com>2006-10-31 18:44:42 -0600
committerKim Phillips <kim.phillips@freescale.com>2006-11-03 19:42:20 -0600
commit2ad6b513b31070bd0c003792ed1c3e7f5d740357 (patch)
treee4d9493e7f6cdc1086a90db4c64bbd265a1acaa6 /include/asm-ppc
parent183da6d9b446cc12123455844ad1187e2375626f (diff)
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mpc83xx: Add support for the MPC8349E-mITX
PREREQUISITE PATCHES: * This patch can only be applied after the following patches have been applied: 1) DNX#2006090742000024 "Add support for multiple I2C buses" 2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x" 3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c" 4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems" 5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems" CHANGELOG: * Add support for the Freescale MPC8349E-mITX reference design platform. The second TSEC (Vitesse 7385 switch) is not supported at this time. Signed-off-by: Timur Tabi <timur@freescale.com>
Diffstat (limited to 'include/asm-ppc')
-rw-r--r--include/asm-ppc/immap_83xx.h16
1 files changed, 16 insertions, 0 deletions
diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
index 40624e8..bc6196c 100644
--- a/include/asm-ppc/immap_83xx.h
+++ b/include/asm-ppc/immap_83xx.h
@@ -82,15 +82,25 @@ typedef struct sysconf83xx {
u8 res5[0x04];
u32 spcr; /* System Priority Configuration Register */
#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable. */
+#define SPCR_PCIHPE_SHIFT (31-3)
#define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority. */
+#define SPCR_PCIPR_SHIFT (31-7)
#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable. */
+#define SPCR_TBEN_SHIFT (31-9)
#define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority. */
+#define SPCR_COREPR_SHIFT (31-11)
#define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority. */
+#define SPCR_TSEC1DP_SHIFT (31-19)
#define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority. */
+#define SPCR_TSEC1BDP_SHIFT (31-21)
#define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority. */
+#define SPCR_TSEC1EP_SHIFT (31-23)
#define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority. */
+#define SPCR_TSEC2DP_SHIFT (31-27)
#define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority. */
+#define SPCR_TSEC2BDP_SHIFT (31-29)
#define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority. */
+#define SPCR_TSEC2EP_SHIFT (31-31)
#define SPCR_RES ~(SPCR_PCIHPE | SPCR_PCIPR | SPCR_TBEN | SPCR_COREPR \
| SPCR_TSEC1DP | SPCR_TSEC1BDP | SPCR_TSEC1EP \
| SPCR_TSEC2DP | SPCR_TSEC2BDP | SPCR_TSEC2EP)
@@ -416,11 +426,17 @@ typedef struct ipic83xx {
typedef struct arbiter83xx {
u32 acr; /* Arbiter Configuration Register */
#define ACR_COREDIS 0x10000000 /* Core disable. */
+#define ACR_COREDIS_SHIFT (31-7)
#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth (number of outstanding transactions). */
+#define ACR_PIPE_DEP_SHIFT (31-15)
#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count. */
+#define ACR_PCI_RPTCNT_SHIFT (31-19)
#define ACR_RPTCNT 0x00000700 /* Repeat count. */
+#define ACR_RPTCNT_SHIFT (31-23)
#define ACR_APARK 0x00000030 /* Address parking. */
+#define ACR_APARK_SHIFT (31-27)
#define ACR_PARKM 0x0000000F /* Parking master. */
+#define ACR_PARKM_SHIFT (31-31)
#define ACR_RES ~(ACR_COREDIS|ACR_PIPE_DEP|ACR_PCI_RPTCNT|ACR_RPTCNT|ACR_APARK|ACR_PARKM)
u32 atr; /* Arbiter Timers Register */
#define ATR_DTO 0x00FF0000 /* Data time out. */