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authorKumar Gala <galak@kernel.crashing.org>2009-01-23 14:22:13 -0600
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2009-01-23 17:08:28 -0600
commitc51fc5d53c4560abc4d0a6126c06fc68133d1528 (patch)
tree37000f5d1602c4c905e626f8af2780ca4b17a0b2 /include/asm-ppc
parent72a9414a8e21e9536822c7353bc08d21ce5ad53d (diff)
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85xx: Handle eLBC difference w/36-bit physical
The eLBC only handles 32-bit physical address in systems with 36-bit physical. The previos generation of LBC handled 34-bit physical address in 36-bit systems. Added a new CONFIG option to convey the difference between the LBC and eLBC. Also added defines for XAM bits used in LBC for the extended 34-bit support. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/asm-ppc')
-rw-r--r--include/asm-ppc/fsl_lbc.h8
1 files changed, 7 insertions, 1 deletions
diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h
index e492c62..9fa0b65 100644
--- a/include/asm-ppc/fsl_lbc.h
+++ b/include/asm-ppc/fsl_lbc.h
@@ -28,6 +28,8 @@
#define BR_BA 0xFFFF8000
#define BR_BA_SHIFT 15
+#define BR_XBA 0x00006000
+#define BR_XBA_SHIFT 13
#define BR_PS 0x00001800
#define BR_PS_SHIFT 11
#define BR_PS_8 0x00000800 /* Port Size 8 bit */
@@ -70,7 +72,7 @@
#endif
/* Convert an address into the right format for the BR registers */
-#ifdef CONFIG_PHYS_64BIT
+#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC)
#define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \
((x & 0x300000000ULL) >> 19)))
#else
@@ -90,6 +92,8 @@
#define OR_GPCM_AM 0xFFFF8000
#define OR_GPCM_AM_SHIFT 15
+#define OR_GPCM_XAM 0x00006000
+#define OR_GPCM_XAM_SHIFT 13
#define OR_GPCM_BCTLD 0x00001000
#define OR_GPCM_BCTLD_SHIFT 12
#define OR_GPCM_CSNT 0x00000800
@@ -132,6 +136,8 @@
#define OR_FCM_AM 0xFFFF8000
#define OR_FCM_AM_SHIFT 15
+#define OR_FCM_XAM 0x00006000
+#define OR_FCM_XAM_SHIFT 13
#define OR_FCM_BCTLD 0x00001000
#define OR_FCM_BCTLD_SHIFT 12
#define OR_FCM_PGS 0x00000400