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authorWolfgang Denk <wd@denx.de>2009-01-24 02:17:02 +0100
committerWolfgang Denk <wd@denx.de>2009-01-24 02:17:02 +0100
commit8f86a3636ef88427f880610638e80991adc41896 (patch)
tree2f6a28872ab9f5de9fec7ac878b8801f5f536eec /include/asm-ppc
parent1ea0823786eb3bbb604da88279eca3ba31ef205f (diff)
parent18af1c5f0f7402dc0d6a71b012c68025dd97cf72 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'include/asm-ppc')
-rw-r--r--include/asm-ppc/fsl_ddr_sdram.h7
-rw-r--r--include/asm-ppc/fsl_lbc.h8
2 files changed, 14 insertions, 1 deletions
diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h
index c1ea7cd..b213af3 100644
--- a/include/asm-ppc/fsl_ddr_sdram.h
+++ b/include/asm-ppc/fsl_ddr_sdram.h
@@ -34,7 +34,10 @@ typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
#elif defined(CONFIG_FSL_DDR3)
#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
+#ifndef CONFIG_FSL_SDRAM_TYPE
+#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
#endif
+#endif /* #if defined(CONFIG_FSL_DDR1) */
/* define bank(chip select) interleaving mode */
#define FSL_DDR_CS0_CS1 0x40
@@ -143,6 +146,10 @@ typedef struct memctl_options_s {
unsigned int bstopre;
unsigned int tCKE_clock_pulse_width_ps; /* tCKE */
unsigned int tFAW_window_four_activates_ps; /* tFAW -- FOUR_ACT */
+
+ /* Automatic self refresh */
+ unsigned int auto_self_refresh_en;
+ unsigned int sr_it;
} memctl_options_t;
extern phys_size_t fsl_ddr_sdram(void);
diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h
index e492c62..9fa0b65 100644
--- a/include/asm-ppc/fsl_lbc.h
+++ b/include/asm-ppc/fsl_lbc.h
@@ -28,6 +28,8 @@
#define BR_BA 0xFFFF8000
#define BR_BA_SHIFT 15
+#define BR_XBA 0x00006000
+#define BR_XBA_SHIFT 13
#define BR_PS 0x00001800
#define BR_PS_SHIFT 11
#define BR_PS_8 0x00000800 /* Port Size 8 bit */
@@ -70,7 +72,7 @@
#endif
/* Convert an address into the right format for the BR registers */
-#ifdef CONFIG_PHYS_64BIT
+#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC)
#define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \
((x & 0x300000000ULL) >> 19)))
#else
@@ -90,6 +92,8 @@
#define OR_GPCM_AM 0xFFFF8000
#define OR_GPCM_AM_SHIFT 15
+#define OR_GPCM_XAM 0x00006000
+#define OR_GPCM_XAM_SHIFT 13
#define OR_GPCM_BCTLD 0x00001000
#define OR_GPCM_BCTLD_SHIFT 12
#define OR_GPCM_CSNT 0x00000800
@@ -132,6 +136,8 @@
#define OR_FCM_AM 0xFFFF8000
#define OR_FCM_AM_SHIFT 15
+#define OR_FCM_XAM 0x00006000
+#define OR_FCM_XAM_SHIFT 13
#define OR_FCM_BCTLD 0x00001000
#define OR_FCM_BCTLD_SHIFT 12
#define OR_FCM_PGS 0x00000400