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authorwdenk <wdenk>2004-07-09 23:27:13 +0000
committerwdenk <wdenk>2004-07-09 23:27:13 +0000
commit0ac6f8b7498d3608bd1de2280a014e9e23d7b1f2 (patch)
treede6ad6c1ee05c1ebcee774a2e8c772e7b2e57586 /include/asm-ppc
parent262381329b87511ed862cde139a3a1ff49e9d7eb (diff)
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Patch by Jon Loeliger, 17 June 2004:
Completion of the 8540ADS/8560ADS updates: Fix some PCI and Rapid I/O memory maps, Initialize both TSEC 1 and 2, Initialize SDRAM Update MAINTAINER for 85xx boards and README.mpc85xxads
Diffstat (limited to 'include/asm-ppc')
-rw-r--r--include/asm-ppc/mmu.h2
-rw-r--r--include/asm-ppc/processor.h41
2 files changed, 40 insertions, 3 deletions
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index 98de51b..2606b79 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -440,7 +440,9 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
#define LAWAR_SIZE 0x0000003F
#define LAWAR_TRGT_IF_PCI 0x00000000
+#define LAWAR_TRGT_IF_PCI1 0x00000000
#define LAWAR_TRGT_IF_PCIX 0x00000000
+#define LAWAR_TRGT_IF_PCI2 0x00100000
#define LAWAR_TRGT_IF_LBC 0x00400000
#define LAWAR_TRGT_IF_CCSR 0x00800000
#define LAWAR_TRGT_IF_RIO 0x00c00000
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 5b3ff75..f7d90f4 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -280,7 +280,6 @@
#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */
#define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */
#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */
-#define SPRN_SVR 0x11E /* System-On-Chip Version Register */
#define SPRN_PVR 0x11F /* Processor Version Register */
#define SPRN_RPA 0x3D6 /* Required Physical Address Register */
#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
@@ -297,6 +296,11 @@
#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
+#ifdef CONFIG_BOOKE
+#define SPRN_SVR 0x3FF /* System Version Register */
+#else
+#define SPRN_SVR 0x11E /* System Version Register */
+#endif
#define SPRN_TBHI 0x3DC /* Time Base High */
#define SPRN_TBHU 0x3CC /* Time Base High User-mode */
#define SPRN_TBLO 0x3DD /* Time Base Low */
@@ -511,6 +515,7 @@
#define SPRG3 SPRN_SPRG3
#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
+#define SVR SPRN_SVR /* System Version Register */
#define TBRL SPRN_TBRL /* Time Base Read Lower Register */
#define TBRU SPRN_TBRU /* Time Base Read Upper Register */
#define TBWL SPRN_TBWL /* Time Base Write Lower Register */
@@ -731,8 +736,11 @@
#define PVR_7400 0x000C0000
#define PVR_7410 0x800C0000
#define PVR_7450 0x80000000
-#define PVR_8540 0x80200010
-#define PVR_8560 0x80200010
+
+#define PVR_85xx 0x80200000
+#define PVR_85xx_REV1 (PVR_85xx | 0x0010)
+#define PVR_85xx_REV2 (PVR_85xx | 0x0020)
+
/*
* For the 8xx processors, all of them report the same PVR family for
@@ -757,6 +765,33 @@
#define PVR_8260_HIP7 0x80822011
#define PVR_8260_HIP7R1 0x80822013
+
+/*
+ * System Version Register
+ */
+
+/* System Version Register (SVR) field extraction */
+
+#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */
+#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */
+
+#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */
+#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */
+
+#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/
+#define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/
+
+
+/*
+ * SVR_VER() Version Values
+ */
+
+#define SVR_8540 0x8030
+#define SVR_8560 0x8070
+#define SVR_8555 0x8079
+#define SVR_8541 0x807A
+
+
/* I am just adding a single entry for 8260 boards. I think we may be
* able to combine mbx, fads, rpxlite, bseip, and classic into a single
* generic 8xx as well. The boards containing these processors are either