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| author | Kumar Gala <galak@kernel.crashing.org> | 2008-04-29 10:27:08 -0500 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2008-04-29 11:44:29 -0500 |
| commit | 45239cf4152109caa925145ccd433529902df887 (patch) | |
| tree | cbeedce4c8e289bf2da8f6a4afa3677f57578ccd /include/asm-ppc | |
| parent | ef7d30b14394e4c4a153118f5845760cadada02a (diff) | |
| download | u-boot-imx-45239cf4152109caa925145ccd433529902df887.zip u-boot-imx-45239cf4152109caa925145ccd433529902df887.tar.gz u-boot-imx-45239cf4152109caa925145ccd433529902df887.tar.bz2 | |
85xx/86xx: Rename ext_refrec to timing_cfg_3 to match docs
All the 85xx and 86xx UM describe the register as timing_cfg_3
not as ext_refrec.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/asm-ppc')
| -rw-r--r-- | include/asm-ppc/immap_85xx.h | 2 | ||||
| -rw-r--r-- | include/asm-ppc/immap_86xx.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index da97cd4..2d07625 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -92,7 +92,7 @@ typedef struct ccsr_ddr { uint cs2_config_2; /* 0x20c8 - DDR Chip Select Configuration 2 */ uint cs3_config_2; /* 0x20cc - DDR Chip Select Configuration 2 */ char res5[48]; - uint ext_refrec; /* 0x2100 - DDR SDRAM Extended Refresh Recovery */ + uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */ uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index 4287cf4..0b78c94 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -109,7 +109,7 @@ typedef struct ccsr_ddr { uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */ uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */ char res7[104]; - uint ext_refrec; /* 0x2100 - DDR SDRAM extended refresh recovery */ + uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */ uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ |