ppc4xx: Consolidate PPC4xx UIC defines

This 2nd patch now removes all UIC mask bit definition. They should be
generated from the vectors by using the UIC_MASK() macro from now on.
This way only the vectors need to get defined for new PPC's.

Also only the really used interrupt vectors are now defined. This makes
definitions for new PPC versions easier and less error prone.

Another part of this patch is that the 4xx emac driver got a little
cleanup, since now the usage of the interrupts is clearer.

Signed-off-by: Stefan Roese <sr@denx.de>

1 files changed, 236 insertions, 412 deletions

diff --git a/include/asm-ppc/ppc4xx-uic.h b/include/asm-ppc/ppc4xx-uic.h
index 1573b1e..b596f0e 100644
--- a/include/asm-ppc/ppc4xx-uic.h
+++ b/include/asm-ppc/ppc4xx-uic.h
@@ -26,444 +26,268 @@
 #ifndef _PPC4xx_UIC_H_
 #define _PPC4xx_UIC_H_
 
-#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-
-/* UIC 0 */
-#define VECNUM_U0                   0  /* UART 0                        */
-#define VECNUM_U1                   1  /* UART 1                        */
-#define VECNUM_IIC0                 2  /* IIC                           */
-#define VECNUM_KRD                  3  /* Kasumi Ready for data         */
-#define VECNUM_KDA                  4  /* Kasumi Data Available         */
-#define VECNUM_PCRW                 5  /* PCI command register write    */
-#define VECNUM_PPM                  6  /* PCI power management          */
-#define VECNUM_IIC1                 7  /* IIC                           */
-#define VECNUM_SPI                  8  /* SPI                           */
-#define VECNUM_EPCISER              9  /* External PCI SERR             */
-#define VECNUM_MTE                 10  /* MAL TXEOB                     */
-#define VECNUM_MRE                 11  /* MAL RXEOB                     */
-#define VECNUM_D0                  12  /* DMA channel 0                 */
-#define VECNUM_D1                  13  /* DMA channel 1                 */
-#define VECNUM_D2                  14  /* DMA channel 2                 */
-#define VECNUM_D3                  15  /* DMA channel 3                 */
-#define VECNUM_UD0                 16  /* UDMA irq 0                    */
-#define VECNUM_UD1                 17  /* UDMA irq 1                    */
-#define VECNUM_UD2                 18  /* UDMA irq 2                    */
-#define VECNUM_UD3                 19  /* UDMA irq 3                    */
-#define VECNUM_HSB2D               20  /* USB2.0 Device                 */
-#define VECNUM_USBDEV		   20  /* USB 1.1/USB 2.0 Device        */
-#define VECNUM_OHCI1               21  /* USB2.0 Host OHCI irq 1        */
-#define VECNUM_OHCI2               22  /* USB2.0 Host OHCI irq 2        */
-#define VECNUM_EIP94               23  /* Security EIP94                */
-#define VECNUM_ETH0                24  /* Emac 0                        */
-#define VECNUM_ETH1                25  /* Emac 1                        */
-#define VECNUM_EHCI                26  /* USB2.0 Host EHCI              */
-#define VECNUM_EIR4                27  /* External interrupt 4          */
-#define VECNUM_UIC2NC              28  /* UIC2 non-critical interrupt   */
-#define VECNUM_UIC2C               29  /* UIC2 critical interrupt       */
-#define VECNUM_UIC1NC              30  /* UIC1 non-critical interrupt   */
-#define VECNUM_UIC1C               31  /* UIC1 critical interrupt       */
-
-/* UIC 1 */
-#define VECNUM_MS           (32 +  0)  /* MAL SERR                      */
-#define VECNUM_MTDE         (32 +  1)  /* MAL TXDE                      */
-#define VECNUM_MRDE         (32 +  2)  /* MAL RXDE                      */
-#define VECNUM_U2           (32 +  3)  /* UART 2                        */
-#define VECNUM_U3           (32 +  4)  /* UART 3                        */
-#define VECNUM_EBCO         (32 +  5)  /* EBCO interrupt status         */
-#define VECNUM_NDFC         (32 +  6)  /* NDFC                          */
-#define VECNUM_KSLE         (32 +  7)  /* KASUMI slave error            */
-#define VECNUM_CT5          (32 +  8)  /* GPT compare timer 5           */
-#define VECNUM_CT6          (32 +  9)  /* GPT compare timer 6           */
-#define VECNUM_PLB34I0      (32 + 10)  /* PLB3X4X MIRQ0                 */
-#define VECNUM_PLB34I1      (32 + 11)  /* PLB3X4X MIRQ1                 */
-#define VECNUM_PLB34I2      (32 + 12)  /* PLB3X4X MIRQ2                 */
-#define VECNUM_PLB34I3      (32 + 13)  /* PLB3X4X MIRQ3                 */
-#define VECNUM_PLB34I4      (32 + 14)  /* PLB3X4X MIRQ4                 */
-#define VECNUM_PLB34I5      (32 + 15)  /* PLB3X4X MIRQ5                 */
-#define VECNUM_CT0          (32 + 16)  /* GPT compare timer 0           */
-#define VECNUM_CT1          (32 + 17)  /* GPT compare timer 1           */
-#define VECNUM_EIR7         (32 + 18)  /* External interrupt 7          */
-#define VECNUM_EIR8         (32 + 19)  /* External interrupt 8          */
-#define VECNUM_EIR9         (32 + 20)  /* External interrupt 9          */
-#define VECNUM_CT2          (32 + 21)  /* GPT compare timer 2           */
-#define VECNUM_CT3          (32 + 22)  /* GPT compare timer 3           */
-#define VECNUM_CT4          (32 + 23)  /* GPT compare timer 4           */
-#define VECNUM_SRE          (32 + 24)  /* Serial ROM error              */
-#define VECNUM_GPTDC        (32 + 25)  /* GPT decrementer pulse         */
-#define VECNUM_RSVD0        (32 + 26)  /* Reserved                      */
-#define VECNUM_EPCIPER      (32 + 27)  /* External PCI PERR             */
-#define VECNUM_EIR0         (32 + 28)  /* External interrupt 0          */
-#define VECNUM_EWU0         (32 + 29)  /* Ethernet 0 wakeup             */
-#define VECNUM_EIR1         (32 + 30)  /* External interrupt 1          */
-#define VECNUM_EWU1         (32 + 31)  /* Ethernet 1 wakeup             */
+/*
+ * Define the number of UIC's
+ */
+#if defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define UIC_MAX		4
+#elif defined(CONFIG_440GX) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+    defined(CONFIG_405EX)
+#define UIC_MAX		3
+#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
+    defined(CONFIG_440EP) || defined(CONFIG_440GR)
+#define UIC_MAX		2
+#else
+#define UIC_MAX		1
+#endif
 
-#define VECNUM_TXDE         VECNUM_MTDE
-#define VECNUM_RXDE         VECNUM_MRDE
+/*
+ * UIC register
+ */
+#define UIC_SR	0x0			/* UIC status			*/
+#define UIC_ER	0x2			/* UIC enable			*/
+#define UIC_CR	0x3			/* UIC critical			*/
+#define UIC_PR	0x4			/* UIC polarity			*/
+#define UIC_TR	0x5			/* UIC triggering		*/
+#define UIC_MSR 0x6			/* UIC masked status		*/
+#define UIC_VR	0x7			/* UIC vector			*/
+#define UIC_VCR 0x8			/* UIC vector configuration	*/
+
+#define UIC0_DCR_BASE 0xc0
+#define uic0sr	(UIC0_DCR_BASE+0x0)	/* UIC0 status			*/
+#define uic0er	(UIC0_DCR_BASE+0x2)	/* UIC0 enable			*/
+#define uic0cr	(UIC0_DCR_BASE+0x3)	/* UIC0 critical		*/
+#define uic0pr	(UIC0_DCR_BASE+0x4)	/* UIC0 polarity		*/
+#define uic0tr	(UIC0_DCR_BASE+0x5)	/* UIC0 triggering		*/
+#define uic0msr (UIC0_DCR_BASE+0x6)	/* UIC0 masked status		*/
+#define uic0vr	(UIC0_DCR_BASE+0x7)	/* UIC0 vector			*/
+#define uic0vcr (UIC0_DCR_BASE+0x8)	/* UIC0 vector configuration	*/
+
+#define UIC1_DCR_BASE 0xd0
+#define uic1sr	(UIC1_DCR_BASE+0x0)	/* UIC1 status			*/
+#define uic1er	(UIC1_DCR_BASE+0x2)	/* UIC1 enable			*/
+#define uic1cr	(UIC1_DCR_BASE+0x3)	/* UIC1 critical		*/
+#define uic1pr	(UIC1_DCR_BASE+0x4)	/* UIC1 polarity		*/
+#define uic1tr	(UIC1_DCR_BASE+0x5)	/* UIC1 triggering		*/
+#define uic1msr (UIC1_DCR_BASE+0x6)	/* UIC1 masked status		*/
+#define uic1vr	(UIC1_DCR_BASE+0x7)	/* UIC1 vector			*/
+#define uic1vcr (UIC1_DCR_BASE+0x8)	/* UIC1 vector configuration	*/
+
+#if defined(CONFIG_440GX)
+#define UIC2_DCR_BASE 0x210
+#else
+#define UIC2_DCR_BASE 0xe0
+#endif
+#define uic2sr	(UIC2_DCR_BASE+0x0)	/* UIC2 status-Read Clear	*/
+#define uic2srs	(UIC2_DCR_BASE+0x1)	/* UIC2 status-Read Set		*/
+#define uic2er	(UIC2_DCR_BASE+0x2)	/* UIC2 enable			*/
+#define uic2cr	(UIC2_DCR_BASE+0x3)	/* UIC2 critical		*/
+#define uic2pr	(UIC2_DCR_BASE+0x4)	/* UIC2 polarity		*/
+#define uic2tr	(UIC2_DCR_BASE+0x5)	/* UIC2 triggering		*/
+#define uic2msr (UIC2_DCR_BASE+0x6)	/* UIC2 masked status		*/
+#define uic2vr	(UIC2_DCR_BASE+0x7)	/* UIC2 vector			*/
+#define uic2vcr (UIC2_DCR_BASE+0x8)	/* UIC2 vector configuration	*/
+
+#define UIC3_DCR_BASE 0xf0
+#define uic3sr	(UIC3_DCR_BASE+0x0)	/* UIC3 status-Read Clear	*/
+#define uic3srs	(UIC3_DCR_BASE+0x1)	/* UIC3 status-Read Set		*/
+#define uic3er	(UIC3_DCR_BASE+0x2)	/* UIC3 enable			*/
+#define uic3cr	(UIC3_DCR_BASE+0x3)	/* UIC3 critical		*/
+#define uic3pr	(UIC3_DCR_BASE+0x4)	/* UIC3 polarity		*/
+#define uic3tr	(UIC3_DCR_BASE+0x5)	/* UIC3 triggering		*/
+#define uic3msr (UIC3_DCR_BASE+0x6)	/* UIC3 masked status		*/
+#define uic3vr	(UIC3_DCR_BASE+0x7)	/* UIC3 vector			*/
+#define uic3vcr (UIC3_DCR_BASE+0x8)	/* UIC3 vector configuration	*/
+
+#if defined(CONFIG_440GX)
+#define UIC_DCR_BASE 0x200
+#define uicb0sr	 (UIC_DCR_BASE+0x0)	/* UIC Base Status Register	*/
+#define uicb0er	 (UIC_DCR_BASE+0x2)	/* UIC Base enable		*/
+#define uicb0cr	 (UIC_DCR_BASE+0x3)	/* UIC Base critical		*/
+#define uicb0pr	 (UIC_DCR_BASE+0x4)	/* UIC Base polarity		*/
+#define uicb0tr	 (UIC_DCR_BASE+0x5)	/* UIC Base triggering		*/
+#define uicb0msr (UIC_DCR_BASE+0x6)	/* UIC Base masked status	*/
+#define uicb0vr	 (UIC_DCR_BASE+0x7)	/* UIC Base vector		*/
+#define uicb0vcr (UIC_DCR_BASE+0x8)	/* UIC Base vector configuration*/
+#endif /* CONFIG_440GX */
+
+/* The following is for compatibility with 405 code */
+#define uicsr  uic0sr
+#define uicer  uic0er
+#define uiccr  uic0cr
+#define uicpr  uic0pr
+#define uictr  uic0tr
+#define uicmsr uic0msr
+#define uicvr  uic0vr
+#define uicvcr uic0vcr
 
-/* UIC 2 */
-#define VECNUM_EIR5         (64 +  0)  /* External interrupt 5          */
-#define VECNUM_EIR6         (64 +  1)  /* External interrupt 6          */
-#define VECNUM_OPB          (64 +  2)  /* OPB to PLB bridge int stat    */
-#define VECNUM_EIR2         (64 +  3)  /* External interrupt 2          */
-#define VECNUM_EIR3         (64 +  4)  /* External interrupt 3          */
-#define VECNUM_DDR2         (64 +  5)  /* DDR2 sdram                    */
-#define VECNUM_MCTX0        (64 +  6)  /* MAl intp coalescence TX0      */
-#define VECNUM_MCTX1        (64 +  7)  /* MAl intp coalescence TX1      */
-#define VECNUM_MCTR0        (64 +  8)  /* MAl intp coalescence TR0      */
-#define VECNUM_MCTR1        (64 +  9)  /* MAl intp coalescence TR1      */
+/*
+ * Now the interrupt vector definitions. They are different for most of
+ * the 4xx variants, so we need some more #ifdef's here. No mask
+ * definitions anymore here. For this please use the UIC_MASK macro below.
+ *
+ * Note: Please only define the interrupts really used in U-Boot here.
+ * Those are the cascading and EMAC/MAL related interrupt.
+ */
 
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_405EP) || defined(CONFIG_405GP)
+#define VECNUM_MAL_SERR		10
+#define VECNUM_MAL_TXEOB	11
+#define VECNUM_MAL_RXEOB	12
+#define VECNUM_MAL_TXDE		13
+#define VECNUM_MAL_RXDE		14
+#define VECNUM_ETH0		15
+#define VECNUM_ETH1_OFFS	2
+#define VECNUM_EIRQ6		29
+#endif /* defined(CONFIG_405EP) */
 
+#if defined(CONFIG_405EZ)
+#define VECNUM_USBDEV		15
+#define VECNUM_ETH0		16
+#define VECNUM_MAL_SERR		18
+#define VECNUM_MAL_TXDE		18
+#define VECNUM_MAL_RXDE		18
+#define VECNUM_MAL_TXEOB	19
+#define VECNUM_MAL_RXEOB	21
+#endif /* CONFIG_405EX */
+
+#if defined(CONFIG_405EX)
 /* UIC 0 */
-#define VECNUM_U1	1		/* UART1			*/
-#define VECNUM_IIC0	2		/* IIC0				*/
-#define VECNUM_IIC1	3		/* IIC1				*/
-#define VECNUM_PIM	4		/* PCI inbound message		*/
-#define VECNUM_PCRW	5		/* PCI command reg write	*/
-#define VECNUM_PPM	6		/* PCI power management		*/
-#define VECNUM_MSI0	8		/* PCI MSI level 0		*/
-#define VECNUM_EIR0	9		/* External interrupt 0		*/
-#define VECNUM_UIC2NC	10		/* UIC2 non-critical interrupt	*/
-#define VECNUM_UIC2C	11		/* UIC2 critical interrupt	*/
-#define VECNUM_D0	12		/* DMA channel 0		*/
-#define VECNUM_D1	13		/* DMA channel 1		*/
-#define VECNUM_D2	14		/* DMA channel 2		*/
-#define VECNUM_D3	15		/* DMA channel 3		*/
-#define VECNUM_UIC3NC	16		/* UIC3 non-critical interrupt	*/
-#define VECNUM_UIC3C	17		/* UIC3 critical interrupt	*/
-#define VECNUM_EIR1	9		/* External interrupt 1		*/
-#define VECNUM_UIC1NC	30		/* UIC1 non-critical interrupt	*/
-#define VECNUM_UIC1C	31		/* UIC1 critical interrupt	*/
+#define VECNUM_MAL_TXEOB	10
+#define VECNUM_MAL_RXEOB	11
+#define VECNUM_ETH0		24
+#define VECNUM_ETH1_OFFS	1
+#define VECNUM_UIC2NCI		28
+#define VECNUM_UIC2CI		29
+#define VECNUM_UIC1NCI		30
+#define VECNUM_UIC1CI		31
 
 /* UIC 1 */
-#define VECNUM_EIR2	(32 + 0)	/* External interrupt 0		*/
-#define VECNUM_U0	(32 + 1)	/* UART0			*/
-#define VECNUM_EIR3	(32 + 20)	/* External interrupt 3		*/
-#define VECNUM_EIR4	(32 + 21)	/* External interrupt 4		*/
-#define VECNUM_EIR5	(32 + 26)	/* External interrupt 5		*/
-#define VECNUM_EIR6	(32 + 27)	/* External interrupt 6		*/
-#define VECNUM_U2	(32 + 28)	/* UART2			*/
-#define VECNUM_U3	(32 + 29)	/* UART3			*/
-#define VECNUM_EIR7	(32 + 30)	/* External interrupt 7		*/
-#define VECNUM_EIR8	(32 + 31)	/* External interrupt 8		*/
-
-/* UIC 2 */
-#define VECNUM_EIR9	(64 + 2)	/* External interrupt 9		*/
-#define VECNUM_MS	(64 + 3)	/* MAL SERR			*/
-#define	VECNUM_TXDE	(64 + 4)	/* MAL TXDE			*/
-#define	VECNUM_RXDE	(64 + 5)	/* MAL RXDE			*/
-#define VECNUM_MTE	(64 + 6)	/* MAL TXEOB			*/
-#define	VECNUM_MRE	(64 + 7)	/* MAL RXEOB			*/
-#define	VECNUM_ETH0	(64 + 16)	/* Ethernet 0			*/
-#define	VECNUM_ETH1	(64 + 17)	/* Ethernet 1			*/
-#define	VECNUM_ETH2	(64 + 18)	/* Ethernet 2			*/
-#define	VECNUM_ETH3	(64 + 19)	/* Ethernet 3			*/
-#define VECNUM_EWU0	(64 + 20)	/* Emac 0 wakeup		*/
-#define VECNUM_EWU1	(64 + 21)	/* Emac 1 wakeup		*/
-#define VECNUM_EWU2	(64 + 22)	/* Emac 2 wakeup		*/
-#define VECNUM_EWU3	(64 + 23)	/* Emac 3 wakeup		*/
-#define VECNUM_EIR10	(64 + 24)	/* External interrupt 10	*/
-#define VECNUM_EIR11	(64 + 25)	/* External interrupt 11	*/
-
-/* UIC 3 */
-#define VECNUM_EIR12	(96 + 20)	/* External interrupt 20	*/
-#define VECNUM_EIR13	(96 + 21)	/* External interrupt 21	*/
-#define VECNUM_EIR14	(96 + 22)	/* External interrupt 22	*/
-#define VECNUM_EIR15	(96 + 23)	/* External interrupt 23	*/
-#define VECNUM_PCIEMSI0	(96 + 24)	/* PCI Express MSI level 0	*/
-#define VECNUM_PCIEMSI1	(96 + 25)	/* PCI Express MSI level 1	*/
-#define VECNUM_PCIEMSI2	(96 + 26)	/* PCI Express MSI level 2	*/
-#define VECNUM_PCIEMSI3	(96 + 27)	/* PCI Express MSI level 3	*/
-#define VECNUM_PCIEMSI4	(96 + 28)	/* PCI Express MSI level 4	*/
-#define VECNUM_PCIEMSI5	(96 + 29)	/* PCI Express MSI level 5	*/
-#define VECNUM_PCIEMSI6	(96 + 30)	/* PCI Express MSI level 6	*/
-#define VECNUM_PCIEMSI7	(96 + 31)	/* PCI Express MSI level 7	*/
-
-#elif defined(CONFIG_440SPE)
+#define VECNUM_MAL_SERR		(32 + 0)
+#define VECNUM_MAL_TXDE		(32 + 1)
+#define VECNUM_MAL_RXDE		(32 + 2)
+#endif /* CONFIG_405EX */
 
+#if defined(CONFIG_440GP) || \
+    defined(CONFIG_440EP) || defined(CONFIG_440GR)
 /* UIC 0 */
-#define VECNUM_U0           0           /* UART0                        */
-#define VECNUM_U1           1           /* UART1                        */
-#define VECNUM_IIC0         2           /* IIC0                         */
-#define VECNUM_IIC1         3           /* IIC1                         */
-#define VECNUM_PIM          4           /* PCI inbound message          */
-#define VECNUM_PCRW         5           /* PCI command reg write        */
-#define VECNUM_PPM          6           /* PCI power management         */
-#define VECNUM_MSI0         7           /* PCI MSI level 0              */
-#define VECNUM_MSI1         8           /* PCI MSI level 0              */
-#define VECNUM_MSI2         9           /* PCI MSI level 0              */
-#define VECNUM_UIC2NC       10          /* UIC2 non-critical interrupt  */
-#define VECNUM_UIC2C        11          /* UIC2 critical interrupt      */
-#define VECNUM_D0           12          /* DMA channel 0                */
-#define VECNUM_D1           13          /* DMA channel 1                */
-#define VECNUM_D2           14          /* DMA channel 2                */
-#define VECNUM_D3           15          /* DMA channel 3                */
-#define VECNUM_UIC3NC       16          /* UIC3 non-critical interrupt  */
-#define VECNUM_UIC3C        17          /* UIC3 critical interrupt      */
-#define VECNUM_UIC1NC       30          /* UIC1 non-critical interrupt  */
-#define VECNUM_UIC1C        31          /* UIC1 critical interrupt      */
+#define VECNUM_MAL_TXEOB	10
+#define VECNUM_MAL_RXEOB	11
+#define VECNUM_UIC1NCI		30
+#define VECNUM_UIC1CI		31
 
 /* UIC 1 */
-#define VECNUM_MS           (32 + 1 )   /* MAL SERR                     */
-#define VECNUM_TXDE         (32 + 2 )   /* MAL TXDE                     */
-#define VECNUM_RXDE         (32 + 3 )   /* MAL RXDE                     */
-#define VECNUM_MTE          (32 + 6 )   /* MAL Tx EOB                   */
-#define VECNUM_MRE          (32 + 7 )   /* MAL Rx EOB                   */
-#define VECNUM_CT0          (32 + 12 )  /* GPT compare timer 0          */
-#define VECNUM_CT1          (32 + 13 )  /* GPT compare timer 1          */
-#define VECNUM_CT2          (32 + 14 )  /* GPT compare timer 2          */
-#define VECNUM_CT3          (32 + 15 )  /* GPT compare timer 3          */
-#define VECNUM_CT4          (32 + 16 )  /* GPT compare timer 4          */
-#define VECNUM_ETH0         (32 + 28)   /* Ethernet interrupt status    */
-#define VECNUM_EWU0         (32 + 29)   /* Emac  wakeup                 */
-
-/* UIC 2 */
-#define VECNUM_EIR5         (64 + 24)   /* External interrupt 5         */
-#define VECNUM_EIR4         (64 + 25)   /* External interrupt 4         */
-#define VECNUM_EIR3         (64 + 26)   /* External interrupt 3         */
-#define VECNUM_EIR2         (64 + 27)   /* External interrupt 2         */
-#define VECNUM_EIR1         (64 + 28)   /* External interrupt 1         */
-#define VECNUM_EIR0         (64 + 29)   /* External interrupt 0         */
-
-#elif defined(CONFIG_440SP)
-
+#define VECNUM_MAL_SERR		(32 + 0)
+#define VECNUM_MAL_TXDE		(32 + 1)
+#define VECNUM_MAL_RXDE		(32 + 2)
+#define VECNUM_USBDEV		(32 + 23)
+#define VECNUM_ETH0		(32 + 28)
+#define VECNUM_ETH1_OFFS	2
+#endif /* CONFIG_440GP */
+
+#if defined(CONFIG_440GX)
 /* UIC 0 */
-#define VECNUM_U0           0           /* UART0                        */
-#define VECNUM_U1           1           /* UART1                        */
-#define VECNUM_IIC0         2           /* IIC0                         */
-#define VECNUM_IIC1         3           /* IIC1                         */
-#define VECNUM_PIM          4           /* PCI inbound message          */
-#define VECNUM_PCRW         5           /* PCI command reg write        */
-#define VECNUM_PPM          6           /* PCI power management         */
-#define VECNUM_UIC1NC       30          /* UIC1 non-critical interrupt  */
-#define VECNUM_UIC1C        31          /* UIC1 critical interrupt      */
+#define VECNUM_MAL_TXEOB	10
+#define VECNUM_MAL_RXEOB	11
 
 /* UIC 1 */
-#define VECNUM_EIR0         (32 + 0)	/* External interrupt 0         */
-#define VECNUM_MS           (32 + 1)	/* MAL SERR                     */
-#define VECNUM_TXDE         (32 + 2)	/* MAL TXDE                     */
-#define VECNUM_RXDE         (32 + 3)	/* MAL RXDE                     */
-#define VECNUM_MTE          (32 + 6)	/* MAL Tx EOB                   */
-#define VECNUM_MRE          (32 + 7)	/* MAL Rx EOB                   */
-#define VECNUM_CT0          (32 + 12)	/* GPT compare timer 0          */
-#define VECNUM_CT1          (32 + 13)	/* GPT compare timer 1          */
-#define VECNUM_CT2          (32 + 14)	/* GPT compare timer 2          */
-#define VECNUM_CT3          (32 + 15)	/* GPT compare timer 3          */
-#define VECNUM_CT4          (32 + 16)	/* GPT compare timer 4          */
-#define VECNUM_ETH0         (32 + 28)	/* Ethernet interrupt status    */
-#define VECNUM_EWU0         (32 + 29)	/* Emac  wakeup                 */
-
-#elif defined(CONFIG_440)
+#define VECNUM_MAL_SERR		(32 + 0)
+#define VECNUM_MAL_TXDE		(32 + 1)
+#define VECNUM_MAL_RXDE		(32 + 2)
+#define VECNUM_ETH0		(32 + 28)
+#define VECNUM_ETH1_OFFS	2
+
+/* UICB 0 (440GX only) */
+#define VECNUM_UIC0CI		0
+#define VECNUM_UIC0NCI		1
+#define VECNUM_UIC1CI		2
+#define VECNUM_UIC1NCI		3
+#define VECNUM_UIC2CI		4
+#define VECNUM_UIC2NCI		5
+#endif /* CONFIG_440GX */
 
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 /* UIC 0 */
-#define VECNUM_U0           0           /* UART0                        */
-#define VECNUM_U1           1           /* UART1                        */
-#define VECNUM_IIC0         2           /* IIC0                         */
-#define VECNUM_IIC1         3           /* IIC1                         */
-#define VECNUM_PIM          4           /* PCI inbound message          */
-#define VECNUM_PCRW         5           /* PCI command reg write        */
-#define VECNUM_PPM          6           /* PCI power management         */
-#define VECNUM_MSI0         7           /* PCI MSI level 0              */
-#define VECNUM_MSI1         8           /* PCI MSI level 0              */
-#define VECNUM_MSI2         9           /* PCI MSI level 0              */
-#define VECNUM_MTE          10          /* MAL TXEOB                    */
-#define VECNUM_MRE          11          /* MAL RXEOB                    */
-#define VECNUM_D0           12          /* DMA channel 0                */
-#define VECNUM_D1           13          /* DMA channel 1                */
-#define VECNUM_D2           14          /* DMA channel 2                */
-#define VECNUM_D3           15          /* DMA channel 3                */
-#define VECNUM_CT0          18          /* GPT compare timer 0          */
-#define VECNUM_CT1          19          /* GPT compare timer 1          */
-#define VECNUM_CT2          20          /* GPT compare timer 2          */
-#define VECNUM_CT3          21          /* GPT compare timer 3          */
-#define VECNUM_CT4          22          /* GPT compare timer 4          */
-#define VECNUM_EIR0         23          /* External interrupt 0         */
-#define VECNUM_EIR1         24          /* External interrupt 1         */
-#define VECNUM_EIR2         25          /* External interrupt 2         */
-#define VECNUM_EIR3         26          /* External interrupt 3         */
-#define VECNUM_EIR4         27          /* External interrupt 4         */
-#define VECNUM_EIR5         28          /* External interrupt 5         */
-#define VECNUM_EIR6         29          /* External interrupt 6         */
-#define VECNUM_UIC1NC       30          /* UIC1 non-critical interrupt  */
-#define VECNUM_UIC1C        31          /* UIC1 critical interrupt      */
+#define VECNUM_MAL_TXEOB	10
+#define VECNUM_MAL_RXEOB	11
+#define VECNUM_USBDEV		20
+#define VECNUM_ETH0		24
+#define VECNUM_ETH1_OFFS	1
+#define VECNUM_UIC2NCI		28
+#define VECNUM_UIC2CI		29
+#define VECNUM_UIC1NCI		30
+#define VECNUM_UIC1CI		31
 
 /* UIC 1 */
-#define VECNUM_MS           (32 + 0 )   /* MAL SERR                     */
-#define VECNUM_TXDE         (32 + 1 )   /* MAL TXDE                     */
-#define VECNUM_RXDE         (32 + 2 )   /* MAL RXDE                     */
-#define VECNUM_USBDEV	    (32 + 23)   /* USB 1.1/USB 2.0 Device       */
-#define VECNUM_ETH0         (32 + 28)   /* Ethernet 0 interrupt status  */
-#define VECNUM_EWU0         (32 + 29)   /* Ethernet 0 wakeup            */
-
-#else /* !defined(CONFIG_440) */
-
-#if defined(CONFIG_405EZ)
-#define VECNUM_D0		0	/* DMA channel 0		*/
-#define VECNUM_D1		1	/* DMA channel 1		*/
-#define VECNUM_D2		2	/* DMA channel 2		*/
-#define VECNUM_D3		3	/* DMA channel 3		*/
-#define VECNUM_1588		4	/* IEEE 1588 network synchronization */
-#define VECNUM_U0		5	/* UART0			*/
-#define VECNUM_U1		6	/* UART1			*/
-#define VECNUM_CAN0		7	/* CAN 0			*/
-#define VECNUM_CAN1		8	/* CAN 1			*/
-#define VECNUM_SPI		9	/* SPI				*/
-#define VECNUM_IIC0		10	/* I2C				*/
-#define VECNUM_CHT0		11	/* Chameleon timer high pri interrupt */
-#define VECNUM_CHT1		12	/* Chameleon timer high pri interrupt */
-#define VECNUM_USBH1		13	/* USB Host 1			*/
-#define VECNUM_USBH2		14	/* USB Host 2			*/
-#define VECNUM_USBDEV		15	/* USB Device			*/
-#define VECNUM_ETH0		16	/* 10/100 Ethernet interrupt status */
-#define VECNUM_EWU0		17	/* Ethernet wakeup sequence detected */
-
-#define VECNUM_MADMAL		18	/* Logical OR of following MadMAL int */
-#define VECNUM_MS		18	/*	MAL_SERR_INT		*/
-#define VECNUM_TXDE		18	/*	MAL_TXDE_INT		*/
-#define VECNUM_RXDE		18	/*	MAL_RXDE_INT		*/
+#define VECNUM_MAL_SERR		(32 + 0)
+#define VECNUM_MAL_TXDE		(32 + 1)
+#define VECNUM_MAL_RXDE		(32 + 2)
 
-#define VECNUM_MTE		19	/* MAL TXEOB			*/
-#define VECNUM_MTE1		20	/* MAL TXEOB1			*/
-#define VECNUM_MRE		21	/* MAL RXEOB			*/
-#define VECNUM_NAND		22	/* NAND Flash controller	*/
-#define VECNUM_ADC		23	/* ADC				*/
-#define VECNUM_DAC		24	/* DAC				*/
-#define VECNUM_OPB2PLB		25	/* OPB to PLB bridge interrupt	*/
-#define VECNUM_RESERVED0	26	/* Reserved			*/
-#define VECNUM_EIR0		27	/* External interrupt 0		*/
-#define VECNUM_EIR1		28	/* External interrupt 1		*/
-#define VECNUM_EIR2		29	/* External interrupt 2		*/
-#define VECNUM_EIR3		30	/* External interrupt 3		*/
-#define VECNUM_EIR4		31	/* External interrupt 4		*/
+/* UIC 2 */
+#define VECNUM_EIRQ2		(64 + 3)
+#endif /* CONFIG_440EPX */
 
-#elif defined(CONFIG_405EX)
+#if defined(CONFIG_440SP)
+/* UIC 0 */
+#define VECNUM_UIC1NCI		30
+#define VECNUM_UIC1CI		31
 
+/* UIC 1 */
+#define VECNUM_MAL_SERR		(32 + 1)
+#define VECNUM_MAL_TXDE		(32 + 2)
+#define VECNUM_MAL_RXDE		(32 + 3)
+#define VECNUM_MAL_TXEOB	(32 + 6)
+#define VECNUM_MAL_RXEOB	(32 + 7)
+#define VECNUM_ETH0		(32 + 28)
+#endif /* CONFIG_440SP */
+
+#if defined(CONFIG_440SPE)
 /* UIC 0 */
-#define VECNUM_U0		00
-#define VECNUM_U1		01
-#define VECNUM_IIC0		02
-#define VECNUM_PKA		03
-#define VECNUM_TRNG		04
-#define VECNUM_EBM		05
-#define VECNUM_BGI		06
-#define VECNUM_IIC1		07
-#define VECNUM_SPI		08
-#define VECNUM_EIR0		09
-#define VECNUM_MTE		10	/* MAL Tx EOB */
-#define VECNUM_MRE		11	/* MAL Rx EOB */
-#define VECNUM_DMA0		12
-#define VECNUM_DMA1		13
-#define VECNUM_DMA2		14
-#define VECNUM_DMA3		15
-#define VECNUM_PCIE0AL		16
-#define VECNUM_PCIE0VPD		17
-#define VECNUM_RPCIE0HRST	18
-#define VECNUM_FPCIE0HRST	19
-#define VECNUM_PCIE0TCR		20
-#define VECNUM_PCIEMSI0		21
-#define VECNUM_PCIEMSI1		22
-#define VECNUM_SECURITY		23
-#define VECNUM_ETH0		24
-#define VECNUM_ETH1		25
-#define VECNUM_PCIEMSI2		26
-#define VECNUM_EIR4		27
-#define VECNUM_UIC2NC		28
-#define VECNUM_UIC2C		29
-#define VECNUM_UIC1NC		30
-#define VECNUM_UIC1C		31
+#define VECNUM_UIC2NCI		10
+#define VECNUM_UIC2CI		11
+#define VECNUM_UIC3NCI		16
+#define VECNUM_UIC3CI		17
+#define VECNUM_UIC1NCI		30
+#define VECNUM_UIC1CI		31
 
 /* UIC 1 */
-#define VECNUM_MS		(32 + 00)	/* MAL SERR */
-#define VECNUM_TXDE		(32 + 01)	/* MAL TXDE */
-#define VECNUM_RXDE		(32 + 02)	/* MAL RXDE */
-#define VECNUM_PCIE0BMVC0	(32 + 03)
-#define VECNUM_PCIE0DCRERR	(32 + 04)
-#define VECNUM_EBC		(32 + 05)
-#define VECNUM_NDFC		(32 + 06)
-#define VECNUM_PCEI1DCRERR	(32 + 07)
-#define VECNUM_CT8		(32 + 08)
-#define VECNUM_CT9		(32 + 09)
-#define VECNUM_PCIE1AL		(32 + 10)
-#define VECNUM_PCIE1VPD		(32 + 11)
-#define VECNUM_RPCE1HRST	(32 + 12)
-#define VECNUM_FPCE1HRST	(32 + 13)
-#define VECNUM_PCIE1TCR		(32 + 14)
-#define VECNUM_PCIE1VC0		(32 + 15)
-#define VECNUM_CT3		(32 + 16)
-#define VECNUM_CT4		(32 + 17)
-#define VECNUM_EIR7		(32 + 18)
-#define VECNUM_EIR8		(32 + 19)
-#define VECNUM_EIR9		(32 + 20)
-#define VECNUM_CT5		(32 + 21)
-#define VECNUM_CT6		(32 + 22)
-#define VECNUM_CT7		(32 + 23)
-#define VECNUM_SROM		(32 + 24)	/* SERIAL ROM */
-#define VECNUM_GPTDECPULS	(32 + 25)	/* GPT Decrement pulse */
-#define VECNUM_EIR2		(32 + 26)
-#define VECNUM_EIR5		(32 + 27)
-#define VECNUM_EIR6		(32 + 28)
-#define VECNUM_EMAC0WAKE	(32 + 29)
-#define VECNUM_EIR1		(32 + 30)
-#define VECNUM_EMAC1WAKE	(32 + 31)
+#define VECNUM_MAL_SERR		(32 + 1)
+#define VECNUM_MAL_TXDE		(32 + 2)
+#define VECNUM_MAL_RXDE		(32 + 3)
+#define VECNUM_MAL_TXEOB	(32 + 6)
+#define VECNUM_MAL_RXEOB	(32 + 7)
+#define VECNUM_ETH0		(32 + 28)
+#endif /* CONFIG_440SPE */
+
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+/* UIC 0 */
+#define VECNUM_UIC2NCI		10
+#define VECNUM_UIC2CI		11
+#define VECNUM_UIC3NCI		16
+#define VECNUM_UIC3CI		17
+#define VECNUM_UIC1NCI		30
+#define VECNUM_UIC1CI		31
 
 /* UIC 2 */
-#define VECNUM_PCIE0INTA	(64 + 00)	/* PCIE0 INTA */
-#define VECNUM_PCIE0INTB	(64 + 01)	/* PCIE0 INTB */
-#define VECNUM_PCIE0INTC	(64 + 02)	/* PCIE0 INTC */
-#define VECNUM_PCIE0INTD	(64 + 03)	/* PCIE0 INTD */
-#define VECNUM_EIR3		(64 + 04)	/* External IRQ 3 */
-#define VECNUM_DDRMCUE		(64 + 05)
-#define VECNUM_DDRMCCE		(64 + 06)
-#define VECNUM_MALINTCOATX0	(64 + 07)	/* Interrupt coalecence TX0 */
-#define VECNUM_MALINTCOATX1	(64 + 08)	/* Interrupt coalecence TX1 */
-#define VECNUM_MALINTCOARX0	(64 + 09)	/* Interrupt coalecence RX0 */
-#define VECNUM_MALINTCOARX1	(64 + 10)	/* Interrupt coalecence RX1 */
-#define VECNUM_PCIE1INTA	(64 + 11)	/* PCIE0 INTA */
-#define VECNUM_PCIE1INTB	(64 + 12)	/* PCIE0 INTB */
-#define VECNUM_PCIE1INTC	(64 + 13)	/* PCIE0 INTC */
-#define VECNUM_PCIE1INTD	(64 + 14)	/* PCIE0 INTD */
-#define VECNUM_RPCIEMSI2	(64 + 15)	/* MSI level 2 */
-#define VECNUM_PCIEMSI3		(64 + 16)	/* MSI level 2 */
-#define VECNUM_PCIEMSI4		(64 + 17)	/* MSI level 2 */
-#define VECNUM_PCIEMSI5		(64 + 18)	/* MSI level 2 */
-#define VECNUM_PCIEMSI6		(64 + 19)	/* MSI level 2 */
-#define VECNUM_PCIEMSI7		(64 + 20)	/* MSI level 2 */
-#define VECNUM_PCIEMSI8		(64 + 21)	/* MSI level 2 */
-#define VECNUM_PCIEMSI9		(64 + 22)	/* MSI level 2 */
-#define VECNUM_PCIEMSI10	(64 + 23)	/* MSI level 2 */
-#define VECNUM_PCIEMSI11	(64 + 24)	/* MSI level 2 */
-#define VECNUM_PCIEMSI12	(64 + 25)	/* MSI level 2 */
-#define VECNUM_PCIEMSI13	(64 + 26)	/* MSI level 2 */
-#define VECNUM_PCIEMSI14	(64 + 27)	/* MSI level 2 */
-#define VECNUM_PCIEMSI15	(64 + 28)	/* MSI level 2 */
-#define VECNUM_PLB4XAHB		(64 + 29)	/* PLBxAHB bridge */
-#define VECNUM_USBWAKE		(64 + 30)	/* USB wakup */
-#define VECNUM_USBOTG		(64 + 31)	/* USB OTG */
+#define VECNUM_MAL_SERR		(64 + 3)
+#define	VECNUM_MAL_TXDE		(64 + 4)
+#define	VECNUM_MAL_RXDE		(64 + 5)
+#define VECNUM_MAL_TXEOB	(64 + 6)
+#define	VECNUM_MAL_RXEOB	(64 + 7)
+#define	VECNUM_ETH0		(64 + 16)
+#define VECNUM_ETH1_OFFS	1
+#endif /* CONFIG_460EX */
+
+#if !defined(VECNUM_ETH1_OFFS)
+#define VECNUM_ETH1_OFFS	1
+#endif
 
-#else	/* !CONFIG_405EZ */
-
-#define VECNUM_U0           0           /* UART0                        */
-#define VECNUM_U1           1           /* UART1                        */
-#define VECNUM_D0           5           /* DMA channel 0                */
-#define VECNUM_D1           6           /* DMA channel 1                */
-#define VECNUM_D2           7           /* DMA channel 2                */
-#define VECNUM_D3           8           /* DMA channel 3                */
-#define VECNUM_EWU0         9           /* Ethernet wakeup              */
-#define VECNUM_MS           10          /* MAL SERR                     */
-#define VECNUM_MTE          11          /* MAL TXEOB                    */
-#define VECNUM_MRE          12          /* MAL RXEOB                    */
-#define VECNUM_TXDE         13          /* MAL TXDE                     */
-#define VECNUM_RXDE         14          /* MAL RXDE                     */
-#define VECNUM_ETH0         15          /* Ethernet interrupt status    */
-#define VECNUM_EIR0         25          /* External interrupt 0         */
-#define VECNUM_EIR1         26          /* External interrupt 1         */
-#define VECNUM_EIR2         27          /* External interrupt 2         */
-#define VECNUM_EIR3         28          /* External interrupt 3         */
-#define VECNUM_EIR4         29          /* External interrupt 4         */
-#define VECNUM_EIR5         30          /* External interrupt 5         */
-#define VECNUM_EIR6         31          /* External interrupt 6         */
-#endif	/* defined(CONFIG_405EZ) */
-
-#endif /* defined(CONFIG_440) */
+/*
+ * Mask definitions (used for example in 4xx_enet.c)
+ */
+#define UIC_MASK(vec)		(0x80000000 >> ((vec) & 0x1f))
+#define UIC_NR(vec)		((vec) >> 5)
 
 #endif /* _PPC4xx_UIC_H_ */