83xx: Add support for fsl_dma driver

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Reviewed-by: Ira W. Snyder <iws@ovro.caltech.edu>
Tested-by: Ira W. Snyder <iws@ovro.caltech.edu>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

3 files changed, 43 insertions, 47 deletions

diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h
index 9c358aa..ca143c7 100644
--- a/include/asm-ppc/config.h
+++ b/include/asm-ppc/config.h
@@ -30,8 +30,9 @@
 #endif
 
 #ifndef CONFIG_FSL_DMA
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) && \
-	(defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
+#if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) &&	\
+	!defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) ||		\
+	(defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)))
 #define CONFIG_FSL_DMA
 #endif
 #endif
diff --git a/include/asm-ppc/fsl_dma.h b/include/asm-ppc/fsl_dma.h
index 043669e..1164191 100644
--- a/include/asm-ppc/fsl_dma.h
+++ b/include/asm-ppc/fsl_dma.h
@@ -27,6 +27,41 @@
 
 #include <asm/types.h>
 
+#ifdef CONFIG_MPC83xx
+typedef struct fsl_dma {
+	uint	mr;		/* DMA mode register */
+#define FSL_DMA_MR_CS		0x00000001	/* Channel start */
+#define FSL_DMA_MR_CC		0x00000002	/* Channel continue */
+#define FSL_DMA_MR_CTM		0x00000004	/* Channel xfer mode */
+#define FSL_DMA_MR_CTM_DIRECT	0x00000004	/* Direct channel xfer mode */
+#define FSL_DMA_MR_EOTIE	0x00000080	/* End-of-transfer interrupt en */
+#define FSL_DMA_MR_PRC_MASK	0x00000c00	/* PCI read command */
+#define FSL_DMA_MR_SAHE		0x00001000	/* Source addr hold enable */
+#define FSL_DMA_MR_DAHE		0x00002000	/* Dest addr hold enable */
+#define FSL_DMA_MR_SAHTS_MASK	0x0000c000	/* Source addr hold xfer size */
+#define FSL_DMA_MR_DAHTS_MASK	0x00030000	/* Dest addr hold xfer size */
+#define FSL_DMA_MR_EMS_EN	0x00040000	/* Ext master start en */
+#define FSL_DMA_MR_IRQS		0x00080000	/* Interrupt steer */
+#define FSL_DMA_MR_DMSEN	0x00100000	/* Direct mode snooping en */
+#define FSL_DMA_MR_BWC_MASK	0x00e00000	/* Bandwidth/pause ctl */
+#define FSL_DMA_MR_DRCNT	0x0f000000	/* DMA request count */
+	uint	sr;		/* DMA status register */
+#define FSL_DMA_SR_EOCDI	0x00000001	/* End-of-chain/direct interrupt */
+#define FSL_DMA_SR_EOSI		0x00000002	/* End-of-segment interrupt */
+#define FSL_DMA_SR_CB		0x00000004	/* Channel busy */
+#define FSL_DMA_SR_TE		0x00000080	/* Transfer error */
+	uint	cdar;		/* DMA current descriptor address register */
+	char	res0[4];
+	uint	sar;		/* DMA source address register */
+	char	res1[4];
+	uint	dar;		/* DMA destination address register */
+	char	res2[4];
+	uint	bcr;		/* DMA byte count register */
+	uint	ndar;		/* DMA next descriptor address register */
+	uint	gsr;		/* DMA general status register (DMA3 ONLY!) */
+	char	res3[84];
+} fsl_dma_t;
+#else
 typedef struct fsl_dma {
 	uint	mr;		/* DMA mode register */
 #define FSL_DMA_MR_CS		0x00000001	/* Channel start */
@@ -93,6 +128,7 @@ typedef struct fsl_dma {
 	uint	dsr;		/* DMA destination stride register */
 	char	res4[56];
 } fsl_dma_t;
+#endif /* !CONFIG_MPC83xx */
 
 #ifdef CONFIG_FSL_DMA
 void dma_init(void);
diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
index 8f945a1..7c6a151 100644
--- a/include/asm-ppc/immap_83xx.h
+++ b/include/asm-ppc/immap_83xx.h
@@ -32,6 +32,7 @@
 #include <asm/fsl_i2c.h>
 #include <asm/mpc8xxx_spi.h>
 #include <asm/fsl_lbc.h>
+#include <asm/fsl_dma.h>
 
 /*
  * Local Access Window
@@ -367,51 +368,7 @@ typedef struct dma83xx {
 	u32 imisr;		/* 0x80 Inbound message interrupt status register */
 	u32 imimr;		/* 0x84 Inbound message interrupt mask register */
 	u32 res4[0x1E];		/* 0x88-0x99 reserved */
-	u32 dmamr0;		/* 0x100 DMA 0 mode register */
-	u32 dmasr0;		/* 0x104 DMA 0 status register */
-	u32 dmacdar0;		/* 0x108 DMA 0 current descriptor address register */
-	u32 res5;		/* 0x10C reserved */
-	u32 dmasar0;		/* 0x110 DMA 0 source address register */
-	u32 res6;		/* 0x114 reserved */
-	u32 dmadar0;		/* 0x118 DMA 0 destination address register */
-	u32 res7;		/* 0x11C reserved */
-	u32 dmabcr0;		/* 0x120 DMA 0 byte count register */
-	u32 dmandar0;		/* 0x124 DMA 0 next descriptor address register */
-	u32 res8[0x16];		/* 0x128-0x179 reserved */
-	u32 dmamr1;		/* 0x180 DMA 1 mode register */
-	u32 dmasr1;		/* 0x184 DMA 1 status register */
-	u32 dmacdar1;		/* 0x188 DMA 1 current descriptor address register */
-	u32 res9;		/* 0x18C reserved */
-	u32 dmasar1;		/* 0x190 DMA 1 source address register */
-	u32 res10;		/* 0x194 reserved */
-	u32 dmadar1;		/* 0x198 DMA 1 destination address register */
-	u32 res11;		/* 0x19C reserved */
-	u32 dmabcr1;		/* 0x1A0 DMA 1 byte count register */
-	u32 dmandar1;		/* 0x1A4 DMA 1 next descriptor address register */
-	u32 res12[0x16];	/* 0x1A8-0x199 reserved */
-	u32 dmamr2;		/* 0x200 DMA 2 mode register */
-	u32 dmasr2;		/* 0x204 DMA 2 status register */
-	u32 dmacdar2;		/* 0x208 DMA 2 current descriptor address register */
-	u32 res13;		/* 0x20C reserved */
-	u32 dmasar2;		/* 0x210 DMA 2 source address register */
-	u32 res14;		/* 0x214 reserved */
-	u32 dmadar2;		/* 0x218 DMA 2 destination address register */
-	u32 res15;		/* 0x21C reserved */
-	u32 dmabcr2;		/* 0x220 DMA 2 byte count register */
-	u32 dmandar2;		/* 0x224 DMA 2 next descriptor address register */
-	u32 res16[0x16];	/* 0x228-0x279 reserved */
-	u32 dmamr3;		/* 0x280 DMA 3 mode register */
-	u32 dmasr3;		/* 0x284 DMA 3 status register */
-	u32 dmacdar3;		/* 0x288 DMA 3 current descriptor address register */
-	u32 res17;		/* 0x28C reserved */
-	u32 dmasar3;		/* 0x290 DMA 3 source address register */
-	u32 res18;		/* 0x294 reserved */
-	u32 dmadar3;		/* 0x298 DMA 3 destination address register */
-	u32 res19;		/* 0x29C reserved */
-	u32 dmabcr3;		/* 0x2A0 DMA 3 byte count register */
-	u32 dmandar3;		/* 0x2A4 DMA 3 next descriptor address register */
-	u32 dmagsr;		/* 0x2A8 DMA general status register */
-	u32 res20[0x15];	/* 0x2AC-0x2FF reserved */
+	struct fsl_dma dma[4];
 } dma83xx_t;
 
 /*
@@ -895,6 +852,8 @@ typedef struct immap {
 } immap_t;
 #endif
 
+#define CONFIG_SYS_MPC83xx_DMA_OFFSET	(0x8000)
+#define CONFIG_SYS_MPC83xx_DMA_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)
 #define CONFIG_SYS_MPC83xx_ESDHC_OFFSET	(0x2e000)
 #define CONFIG_SYS_MPC83xx_ESDHC_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
 #define CONFIG_SYS_MPC83xx_USB_OFFSET	0x23000