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| author | Stefan Roese <sr@denx.de> | 2008-07-18 12:24:41 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-07-18 12:31:25 +0200 |
| commit | 60204d06ed9f8c2a67cc79eb67fd2b1d22bcbc8c (patch) | |
| tree | 922577031775f896fe4c2e8a777cb2090b9b10f8 /include/asm-ppc/xilinx_irq.h | |
| parent | 086511fc96a8a9bb56e5e19a3d84c40f4dba80cc (diff) | |
| download | u-boot-imx-60204d06ed9f8c2a67cc79eb67fd2b1d22bcbc8c.zip u-boot-imx-60204d06ed9f8c2a67cc79eb67fd2b1d22bcbc8c.tar.gz u-boot-imx-60204d06ed9f8c2a67cc79eb67fd2b1d22bcbc8c.tar.bz2 | |
ppc4xx: Minor coding style cleanup of Xilinx Virtex5 ml507 support
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/asm-ppc/xilinx_irq.h')
| -rw-r--r-- | include/asm-ppc/xilinx_irq.h | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/include/asm-ppc/xilinx_irq.h b/include/asm-ppc/xilinx_irq.h index ddccc75..61171c2 100644 --- a/include/asm-ppc/xilinx_irq.h +++ b/include/asm-ppc/xilinx_irq.h @@ -19,18 +19,18 @@ #ifndef XILINX_IRQ_H #define XILINX_IRQ_H -#define intc XPAR_INTC_0_BASEADDR -#define ISR (intc+(0*4)) /* Interrupt Status Register */ -#define IPR (intc+(1*4)) /* Interrupt Pending Register */ -#define IER (intc+(2*4)) /* Interrupt Enable Register */ -#define IAR (intc+(3*4)) /* Interrupt Acknowledge Register */ -#define SIE (intc+(4*4)) /* Set Interrupt Enable bits */ -#define CIE (intc+(5*4)) /* Clear Interrupt Enable bits */ -#define IVR (intc+(6*4)) /* Interrupt Vector Register */ -#define MER (intc+(7*4)) /* Master Enable Register */ +#define intc XPAR_INTC_0_BASEADDR +#define ISR (intc + (0 * 4)) /* Interrupt Status Register */ +#define IPR (intc + (1 * 4)) /* Interrupt Pending Register */ +#define IER (intc + (2 * 4)) /* Interrupt Enable Register */ +#define IAR (intc + (3 * 4)) /* Interrupt Acknowledge Register */ +#define SIE (intc + (4 * 4)) /* Set Interrupt Enable bits */ +#define CIE (intc + (5 * 4)) /* Clear Interrupt Enable bits */ +#define IVR (intc + (6 * 4)) /* Interrupt Vector Register */ +#define MER (intc + (7 * 4)) /* Master Enable Register */ -#define IRQ_MASK(irq) (1<<(irq&0x1f)) +#define IRQ_MASK(irq) (1 << (irq & 0x1f)) -#define IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS +#define IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS #endif |