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| author | Kumar Gala <galak@kernel.crashing.org> | 2009-02-06 09:56:35 -0600 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2009-02-16 18:05:51 -0600 |
| commit | f8523cb0815b2d3d2d780b7d49ca614105555f58 (patch) | |
| tree | 206a783a630f0878ad49977dfe712219bfd4e957 /include/asm-ppc/processor.h | |
| parent | 1542fbdeec0d1e2a6df13189df8dcb1ce8802be3 (diff) | |
| download | u-boot-imx-f8523cb0815b2d3d2d780b7d49ca614105555f58.zip u-boot-imx-f8523cb0815b2d3d2d780b7d49ca614105555f58.tar.gz u-boot-imx-f8523cb0815b2d3d2d780b7d49ca614105555f58.tar.bz2 | |
85xx: Fix how we map DDR memory
Previously we only allowed power-of-two memory sizes and didnt
handle >2G of memory. Now we will map up to CONFIG_MAX_MEM_MAPPED
and should properly handle any size that we can make in the TLBs
we have available to us
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include/asm-ppc/processor.h')
| -rw-r--r-- | include/asm-ppc/processor.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index e07e5d3..4203ada 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -451,6 +451,8 @@ #define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */ #define SPRN_L2CSR1 0x3fa /* L2 Data Cache Control and Status Register 1 */ +#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ +#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ #define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */ #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ |