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| author | Stefan Roese <sr@denx.de> | 2007-08-21 16:33:33 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-08-21 16:33:33 +0200 |
| commit | 93f798346033a1f6d22090b47abad4be88243b04 (patch) | |
| tree | 45b4d2a887a89572015de3234b04b419bfc11b44 /include/asm-ppc/processor.h | |
| parent | 3ad63878737a5a2b1e60825bf0a7d601d7a695e7 (diff) | |
| parent | 3e66c078003607a7d1d214c15a5f262bc1b4032f (diff) | |
| download | u-boot-imx-93f798346033a1f6d22090b47abad4be88243b04.zip u-boot-imx-93f798346033a1f6d22090b47abad4be88243b04.tar.gz u-boot-imx-93f798346033a1f6d22090b47abad4be88243b04.tar.bz2 | |
Merge with /home/stefan/git/u-boot/u-boot-ppc4xx
Diffstat (limited to 'include/asm-ppc/processor.h')
| -rw-r--r-- | include/asm-ppc/processor.h | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 4898dd4..0a160e2 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -58,7 +58,6 @@ #else #define MSR_KERNEL MSR_ME #endif -#define MSR_USER MSR_KERNEL|MSR_PR|MSR_EE /* Floating Point Status and Control Register (FPSCR) Fields */ @@ -218,12 +217,14 @@ #define HID0_DPM (1<<20) #define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */ #define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */ +#define HID0_TBEN (1<<14) /* Time Base Enable */ #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ #define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */ #define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ #define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */ #define HID0_DCI HID0_DCFI #define HID0_SPD (1<<9) /* Speculative disable */ +#define HID0_ENMAS7 (1<<7) /* Enable MAS7 Update for 36-bit phys */ #define HID0_SGE (1<<7) /* Store Gathering Enable */ #define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */ #define HID0_DCFA (1<<6) /* Data Cache Flush Assist */ @@ -451,6 +452,7 @@ #define SPRN_PID1 0x279 /* Process ID Register 1 */ #define SPRN_PID2 0x27a /* Process ID Register 2 */ #define SPRN_MCSR 0x23c /* Machine Check Syndrome register */ +#define SPRN_MCAR 0x23d /* Machine Check Address register */ #ifdef CONFIG_440 #define MCSR_MCS 0x80000000 /* Machine Check Summary */ #define MCSR_IB 0x40000000 /* Instruction PLB Error */ @@ -465,7 +467,8 @@ #define ESR_ST 0x00800000 /* Store Operation */ #if defined(CONFIG_MPC86xx) -#define SPRN_MSSCRO 0x3f6 +#define SPRN_MSSCR0 0x3f6 +#define SPRN_MSSSR0 0x3f7 #endif @@ -532,7 +535,7 @@ #define LR SPRN_LR #define MBAR SPRN_MBAR /* System memory base address */ #if defined(CONFIG_MPC86xx) -#define MSSCR0 SPRN_MSSCRO +#define MSSCR0 SPRN_MSSCR0 #endif #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) #define PIR SPRN_PIR |