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authorEran Liberty <liberty@freescale.com>2005-07-28 10:08:46 -0500
committerJon Loeliger <jdl@freescale.com>2005-07-28 10:08:46 -0500
commitf046ccd15c8bc9613bfd72916b761a127d36e5c6 (patch)
tree40b48bdc1fff75c661cab5c4806a322a67e9dc44 /include/asm-ppc/processor.h
parent63be111e72371b6edc6d02134dd785abb6be188c (diff)
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* Patch by Eran Liberty
Add support for the Freescale MPC8349ADS board.
Diffstat (limited to 'include/asm-ppc/processor.h')
-rw-r--r--include/asm-ppc/processor.h11
1 files changed, 8 insertions, 3 deletions
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 20949dc..d4404c1 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -200,6 +200,11 @@
#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
+
+#define HID0_ICE_SHIFT 15
+#define HID0_DCE_SHIFT 14
+#define HID0_DLOCK_SHIFT 12
+
#define HID0_EMCP (1<<31) /* Enable Machine Check pin */
#define HID0_EBA (1<<29) /* Enable Bus Address Parity */
#define HID0_EBD (1<<28) /* Enable Bus Data Parity */
@@ -211,10 +216,10 @@
#define HID0_NAP (1<<22)
#define HID0_SLEEP (1<<21)
#define HID0_DPM (1<<20)
-#define HID0_ICE (1<<15) /* Instruction Cache Enable */
-#define HID0_DCE (1<<14) /* Data Cache Enable */
+#define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */
+#define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */
#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
-#define HID0_DLOCK (1<<12) /* Data Cache Lock */
+#define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */
#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
#define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */
#define HID0_DCI HID0_DCFI