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| author | Markus Klotzbuecher <mk@denx.de> | 2007-05-07 14:10:38 +0200 |
|---|---|---|
| committer | Markus Klotzbuecher <mk@pollux.denx.de> | 2007-05-07 14:10:38 +0200 |
| commit | 6ede0c8b69ad1e6b16463ec75a6dccca152c4b17 (patch) | |
| tree | 978dcbd6189998876bb227ae5bbea03000a2f9c5 /include/asm-ppc/processor.h | |
| parent | 61ea75aa07838435ec570ac85a2e3fc038844596 (diff) | |
| parent | ac4cd59d59c9bf3f89cb7a344abf8184d678f562 (diff) | |
| download | u-boot-imx-6ede0c8b69ad1e6b16463ec75a6dccca152c4b17.zip u-boot-imx-6ede0c8b69ad1e6b16463ec75a6dccca152c4b17.tar.gz u-boot-imx-6ede0c8b69ad1e6b16463ec75a6dccca152c4b17.tar.bz2 | |
Merge with git://www.denx.de/git/u-boot.git
Diffstat (limited to 'include/asm-ppc/processor.h')
| -rw-r--r-- | include/asm-ppc/processor.h | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 0585962..5efc3ee 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -232,6 +232,9 @@ #define HID0_BHTE (1<<2) /* Branch History Table Enable */ #define HID0_BTCD (1<<1) /* Branch target cache disable */ #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ +#define HID1_RFXE (1<<17) /* Read Fault Exception Enable */ +#define HID1_ASTME (1<<13) /* Address bus streaming mode */ +#define HID1_ABE (1<<12) /* Address broadcast enable */ #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ #ifndef CONFIG_BOOKE #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ @@ -415,10 +418,12 @@ #define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */ /* e500 definitions */ -#define SPRN_L1CSR0 0x3f2 /* L1 Cache Control and Status Register 0 */ +#define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */ +#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ -#define SPRN_L1CSR1 0x3f3 /* L1 Cache Control and Status Register 1 */ +#define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */ +#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ @@ -701,8 +706,6 @@ #define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */ #define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */ -/* System-On-Chip Version Numbers (version field only) */ -#define SVR_MPC5200 0x8011 /* Processor Version Register */ @@ -813,6 +816,12 @@ #define PVR_8260_HIP7R1 0x80822013 #define PVR_8260_HIP7RA 0x80822014 +/* + * MPC 52xx + */ +#define PVR_5200 0x80822011 +#define PVR_5200B 0x80822014 + /* * System Version Register @@ -840,9 +849,12 @@ #define SVR_8560 0x8070 #define SVR_8555 0x8079 #define SVR_8541 0x807A +#define SVR_8544 0x8034 +#define SVR_8544_E 0x803C #define SVR_8548 0x8031 #define SVR_8548_E 0x8039 #define SVR_8641 0x8090 +#define SVR_8568_E 0x807D /* I am just adding a single entry for 8260 boards. I think we may be |