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| author | Stefan Roese <sr@denx.de> | 2008-07-09 17:33:57 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-07-10 09:14:01 +0200 |
| commit | 5d812b8b4ad9667c77a5bf92b4ba81699abc9fc3 (patch) | |
| tree | 08dd2c7f7496d9f160d14bb94ec3d2776b783051 /include/asm-ppc/ppc4xx-sdram.h | |
| parent | cf1c2ed91df26903b956948f37f82de9e1158a89 (diff) | |
| download | u-boot-imx-5d812b8b4ad9667c77a5bf92b4ba81699abc9fc3.zip u-boot-imx-5d812b8b4ad9667c77a5bf92b4ba81699abc9fc3.tar.gz u-boot-imx-5d812b8b4ad9667c77a5bf92b4ba81699abc9fc3.tar.bz2 | |
ppc4xx: Enable support for > 2GB SDRAM on AMCC Katmai
Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
To support such configurations, we "only" map the first 2GB via the TLB's. We
need some free virtual address space for the remaining peripherals like, SoC
devices, FLASH etc.
Note that ECC is currently not supported on configurations with more than 2GB
SDRAM. This is because we only map the first 2GB on such systems, and therefore
the ECC parity byte of the remaining area can't be written.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include/asm-ppc/ppc4xx-sdram.h')
| -rw-r--r-- | include/asm-ppc/ppc4xx-sdram.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index 83931f1..e151f0c 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -284,8 +284,8 @@ #if defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) #define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */ -#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((u32)(n))&0xFFE00000)>>2) -#define SDRAM_RXBAS_SDBA_DECODE(n) ((((u32)(n))&0xFFE00000)<<2) +#define SDRAM_RXBAS_SDBA_ENCODE(n) ((u32)(((phys_size_t)(n) >> 2) & 0xFFE00000)) +#define SDRAM_RXBAS_SDBA_DECODE(n) ((((phys_size_t)(n)) & 0xFFE00000) << 2) #endif /* CONFIG_440SPE */ #if defined(CONFIG_440SP) #define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */ |