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author | Wolfgang Denk <wd@pollux.denx.de> | 2006-10-20 23:52:58 +0200 |
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committer | Wolfgang Denk <wd@pollux.denx.de> | 2006-10-20 23:52:58 +0200 |
commit | d67c14c0f4e390dc7069bbe852f5ec8ea1acc8fc (patch) | |
tree | 8eecbb0f2c98e2619abe8eafb3cbae188d4e6e30 /include/asm-ppc/mmu.h | |
parent | ba999c531ed16ec749b2b6f4b0133cee38842b91 (diff) | |
parent | 3acb7727ce6aa403e938e7cf3761924590bead47 (diff) | |
download | u-boot-imx-d67c14c0f4e390dc7069bbe852f5ec8ea1acc8fc.zip u-boot-imx-d67c14c0f4e390dc7069bbe852f5ec8ea1acc8fc.tar.gz u-boot-imx-d67c14c0f4e390dc7069bbe852f5ec8ea1acc8fc.tar.bz2 |
Merge with http://www.jdl.com/software/u-boot-86xx.git
Diffstat (limited to 'include/asm-ppc/mmu.h')
-rw-r--r-- | include/asm-ppc/mmu.h | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index baaf6f7..914f28b 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -117,8 +117,8 @@ typedef struct _P601_BAT { */ typedef struct _pte { - unsigned long page_num:20; - unsigned long flags:12; /* Page flags (some unused bits) */ + unsigned long page_num:20; + unsigned long flags:12; /* Page flags (some unused bits) */ } pte; #define PD_SHIFT (10+12) /* Page directory */ @@ -434,9 +434,14 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define BOOKE_PAGESZ_1GB 10 #define BOOKE_PAGESZ_4GB 11 +#if defined(CONFIG_MPC86xx) +#define LAWBAR_BASE_ADDR 0x00FFFFFF +#define LAWAR_TRGT_IF 0x01F00000 +#else #define LAWBAR_BASE_ADDR 0x000FFFFF -#define LAWAR_EN 0x80000000 #define LAWAR_TRGT_IF 0x00F00000 +#endif +#define LAWAR_EN 0x80000000 #define LAWAR_SIZE 0x0000003F #define LAWAR_TRGT_IF_PCI 0x00000000 @@ -445,8 +450,11 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define LAWAR_TRGT_IF_PCI2 0x00100000 #define LAWAR_TRGT_IF_LBC 0x00400000 #define LAWAR_TRGT_IF_CCSR 0x00800000 +#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000 #define LAWAR_TRGT_IF_RIO 0x00c00000 #define LAWAR_TRGT_IF_DDR 0x00f00000 +#define LAWAR_TRGT_IF_DDR1 0x00f00000 +#define LAWAR_TRGT_IF_DDR2 0x01600000 #define LAWAR_SIZE_BASE 0xa #define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1) @@ -469,6 +477,10 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); #define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18) #define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19) #define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20) +#define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21) +#define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22) +#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23) +#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24) #ifdef CONFIG_440SPE /*----------------------------------------------------------------------------+ |