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authorKumar Gala <galak@kernel.crashing.org>2008-08-12 11:14:19 -0500
committerKumar Gala <galak@kernel.crashing.org>2008-08-27 11:43:54 -0500
commitef50d6c06ece74fb17e8d7510e62cad9df8b810d (patch)
tree60390a7fb3d9cd7d4d6837a5f9d6135edf110b41 /include/asm-ppc/immap_85xx.h
parent129ba616b3813dde861f25f3d8a3c47c5c36ad5f (diff)
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mpc85xx: Add support for the MPC8536
The MPC8536 Adds SDHC and SATA controllers to the PQ3 family. We also have SERDES init code for the 8536. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dejan Minic <minic@freescale.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com>
Diffstat (limited to 'include/asm-ppc/immap_85xx.h')
-rw-r--r--include/asm-ppc/immap_85xx.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 113ba48..559d6ea 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1560,6 +1560,7 @@ typedef struct ccsr_gur {
#define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
+#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
#define MPC85xx_PORDEVSR_IO_SEL 0x00380000
#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
@@ -1653,13 +1654,23 @@ typedef struct ccsr_gur {
#define CFG_MPC85xx_PCIX_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX_OFFSET)
#define CFG_MPC85xx_PCIX2_OFFSET (0x9000)
#define CFG_MPC85xx_PCIX2_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX2_OFFSET)
+#define CFG_MPC85xx_SATA1_OFFSET (0x18000)
+#define CFG_MPC85xx_SATA1_ADDR (CFG_IMMR + CFG_MPC85xx_SATA1_OFFSET)
+#define CFG_MPC85xx_SATA2_OFFSET (0x19000)
+#define CFG_MPC85xx_SATA2_ADDR (CFG_IMMR + CFG_MPC85xx_SATA2_OFFSET)
#define CFG_MPC85xx_L2_OFFSET (0x20000)
#define CFG_MPC85xx_L2_ADDR (CFG_IMMR + CFG_MPC85xx_L2_OFFSET)
#define CFG_MPC85xx_DMA_OFFSET (0x21000)
#define CFG_MPC85xx_DMA_ADDR (CFG_IMMR + CFG_MPC85xx_DMA_OFFSET)
+#define CFG_MPC85xx_ESDHC_OFFSET (0x2e000)
+#define CFG_MPC85xx_ESDHC_ADDR (CFG_IMMR + CFG_MPC85xx_ESDHC_OFFSET)
#define CFG_MPC85xx_PIC_OFFSET (0x40000)
#define CFG_MPC85xx_PIC_ADDR (CFG_IMMR + CFG_MPC85xx_PIC_OFFSET)
#define CFG_MPC85xx_CPM_OFFSET (0x80000)
#define CFG_MPC85xx_CPM_ADDR (CFG_IMMR + CFG_MPC85xx_CPM_OFFSET)
+#define CFG_MPC85xx_SERDES1_OFFSET (0xE3000)
+#define CFG_MPC85xx_SERDES1_ADDR (CFG_IMMR + CFG_MPC85xx_SERDES2_OFFSET)
+#define CFG_MPC85xx_SERDES2_OFFSET (0xE3100)
+#define CFG_MPC85xx_SERDES2_ADDR (CFG_IMMR + CFG_MPC85xx_SERDES2_OFFSET)
#endif /*__IMMAP_85xx__*/