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author | Markus Klotzbuecher <mk@denx.de> | 2008-01-09 13:57:10 +0100 |
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committer | Markus Klotzbuecher <mk@denx.de> | 2008-01-09 13:57:10 +0100 |
commit | 6a40ef62c4300e9f606deef0a4618cbc4b514a51 (patch) | |
tree | c01bdd0e773d092f13af05567fa92fb9072df9e0 /include/asm-ppc/gpio.h | |
parent | 245a362ad3c0c1b84fccc9fec7b623eb14f6e502 (diff) | |
parent | 07eb02687f008721974a2fb54cd7fdc28033ab3c (diff) | |
download | u-boot-imx-6a40ef62c4300e9f606deef0a4618cbc4b514a51.zip u-boot-imx-6a40ef62c4300e9f606deef0a4618cbc4b514a51.tar.gz u-boot-imx-6a40ef62c4300e9f606deef0a4618cbc4b514a51.tar.bz2 |
Merge git://www.denx.de/git/u-boot
Conflicts:
board/tqm5200/tqm5200.c
Diffstat (limited to 'include/asm-ppc/gpio.h')
-rw-r--r-- | include/asm-ppc/gpio.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/include/asm-ppc/gpio.h b/include/asm-ppc/gpio.h index c9b6a36..c3a4a88 100644 --- a/include/asm-ppc/gpio.h +++ b/include/asm-ppc/gpio.h @@ -21,6 +21,9 @@ * MA 02111-1307 USA */ +#ifndef __ASM_PPC_GPIO_H +#define __ASM_PPC_GPIO_H + /* 4xx PPC's have 2 GPIO controllers */ #if defined(CONFIG_405EZ) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ @@ -30,6 +33,36 @@ #define GPIO_GROUP_MAX 1 #endif +/* Offsets */ +#define GPIOx_OR 0x00 /* GPIO Output Register */ +#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */ +#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */ +#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */ +#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */ +#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */ +#define GPIOx_ODR 0x18 /* GPIO Open drain Register */ +#define GPIOx_IR 0x1C /* GPIO Input Register */ +#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */ +#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */ +#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */ +#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */ +#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */ +#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */ +#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */ +#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */ +#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */ + +#define GPIO_OR(x) (x+GPIOx_OR) /* GPIO Output Register */ +#define GPIO_TCR(x) (x+GPIOx_TCR) /* GPIO Three-State Control Register */ +#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Select Register High or Low */ +#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */ +#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */ +#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */ +#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */ + +#define GPIO0 0 +#define GPIO1 1 + #define GPIO_MAX 32 #define GPIO_ALT1_SEL 0x40000000 #define GPIO_ALT2_SEL 0x80000000 @@ -55,4 +88,7 @@ typedef struct { void gpio_config(int pin, int in_out, int gpio_alt, int out_val); void gpio_write_bit(int pin, int val); int gpio_read_out_bit(int pin); +int gpio_read_in_bit(int pin); void gpio_set_chip_configuration(void); + +#endif /* __ASM_PPC_GPIO_H */ |