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| author | Kumar Gala <galak@kernel.crashing.org> | 2009-09-15 22:21:58 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-09-24 12:04:57 -0500 |
| commit | 202d94875c98b7b573f136c4f353609758ed9733 (patch) | |
| tree | e0af514570c712830620de7fb014415504da698c /include/asm-ppc/fsl_lbc.h | |
| parent | 30d7aae7e82dacf9ae2983fbbf3567515266968b (diff) | |
| download | u-boot-imx-202d94875c98b7b573f136c4f353609758ed9733.zip u-boot-imx-202d94875c98b7b573f136c4f353609758ed9733.tar.gz u-boot-imx-202d94875c98b7b573f136c4f353609758ed9733.tar.bz2 | |
ppc/85xx: Fix LCRR_CLKDIV defines
For some reason the CLKDIV field varies between SoC in how it interprets
the bit values.
All 83xx and early (e500v1) PQ3 devices support:
clk/2: CLKDIV = 2
clk/4: CLKDIV = 4
clk/8: CLKDIV = 8
Newer PQ3 (e500v2) and MPC86xx support:
clk/4: CLKDIV = 2
clk/8: CLKDIV = 4
clk/16: CLKDIV = 8
Ensure that the MPC86xx and MPC85xx still get the same behavior and make
the defines reflect their logical view (not the value of the field).
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Peter Tyser <ptyser@xes-inc.com>
Diffstat (limited to 'include/asm-ppc/fsl_lbc.h')
| -rw-r--r-- | include/asm-ppc/fsl_lbc.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h index a28082e..08d31e1 100644 --- a/include/asm-ppc/fsl_lbc.h +++ b/include/asm-ppc/fsl_lbc.h @@ -311,9 +311,17 @@ */ #define LCRR_CLKDIV 0x0000001F #define LCRR_CLKDIV_SHIFT 0 +#if defined(CONFIG_MPC83xx) || defined (CONFIG_MPC8540) || \ + defined(CONFIG_MPC8541) || defined (CONFIG_MPC8555) || \ + defined(CONFIG_MPC8560) #define LCRR_CLKDIV_2 0x00000002 #define LCRR_CLKDIV_4 0x00000004 #define LCRR_CLKDIV_8 0x00000008 +#else +#define LCRR_CLKDIV_4 0x00000002 +#define LCRR_CLKDIV_8 0x00000004 +#define LCRR_CLKDIV_16 0x00000008 +#endif /* LTEDR - Transfer Error Check Disable Register */ |