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authorDave Liu <daveliu@freescale.com>2009-03-14 12:48:30 +0800
committerKumar Gala <galak@kernel.crashing.org>2009-03-30 13:33:50 -0500
commitc360ceac0286159f94d9d1a9496fc9858c8d9bec (patch)
treefdd1868af478993fdb547171665c5c517ee6c071 /include/asm-ppc/fsl_ddr_dimm_params.h
parent6a8197836702991468cead5ead073f589e2623ad (diff)
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fsl-ddr: add the DDR3 SPD infrastructure
- support mirrored DIMMs, not support register DIMMs - test passed on P2020DS board with MT9JSF12872AY-1G1D1 - test passed on MPC8569MDS board with MT8JSF12864HY-1G1D1 Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Travis Wheatley <travis.wheatley@freescale.com>
Diffstat (limited to 'include/asm-ppc/fsl_ddr_dimm_params.h')
-rw-r--r--include/asm-ppc/fsl_ddr_dimm_params.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/include/asm-ppc/fsl_ddr_dimm_params.h b/include/asm-ppc/fsl_ddr_dimm_params.h
index c794eed..55923e0 100644
--- a/include/asm-ppc/fsl_ddr_dimm_params.h
+++ b/include/asm-ppc/fsl_ddr_dimm_params.h
@@ -33,9 +33,15 @@ typedef struct dimm_params_s {
/* used in computing base address of DIMMs */
unsigned long long base_address;
+ /* mirrored DIMMs */
+ unsigned int mirrored_dimm; /* only for ddr3 */
/* DIMM timing parameters */
+ unsigned int mtb_ps; /* medium timebase ps, only for ddr3 */
+ unsigned int tAA_ps; /* minimum CAS latency time, only for ddr3 */
+ unsigned int tFAW_ps; /* four active window delay, only for ddr3 */
+
/*
* SDRAM clock periods
* The range for these are 1000-10000 so a short should be sufficient
@@ -67,6 +73,7 @@ typedef struct dimm_params_s {
unsigned int refresh_rate_ps;
+ /* DDR3 doesn't need these as below */
unsigned int tIS_ps; /* byte 32, spd->ca_setup */
unsigned int tIH_ps; /* byte 33, spd->ca_hold */
unsigned int tDS_ps; /* byte 34, spd->data_setup */