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| author | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2008-12-17 16:53:07 +0100 |
|---|---|---|
| committer | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2008-12-17 16:53:07 +0100 |
| commit | cb5473205206c7f14cbb1e747f28ec75b48826e2 (patch) | |
| tree | 8f4808d60917100b18a10b05230f7638a0a9bbcc /include/asm-ppc/4xx_pcie.h | |
| parent | baf449fc5ff96f071bb0e3789fd3265f6d4fd9a0 (diff) | |
| parent | 92c78a3bbcb2ce508b4bf1c4a1e0940406a024bb (diff) | |
| download | u-boot-imx-cb5473205206c7f14cbb1e747f28ec75b48826e2.zip u-boot-imx-cb5473205206c7f14cbb1e747f28ec75b48826e2.tar.gz u-boot-imx-cb5473205206c7f14cbb1e747f28ec75b48826e2.tar.bz2 | |
Merge branch 'fixes' into cleanups
Conflicts:
board/atmel/atngw100/atngw100.c
board/atmel/atstk1000/atstk1000.c
cpu/at32ap/at32ap700x/gpio.c
include/asm-avr32/arch-at32ap700x/clk.h
include/configs/atngw100.h
include/configs/atstk1002.h
include/configs/atstk1003.h
include/configs/atstk1004.h
include/configs/atstk1006.h
include/configs/favr-32-ezkit.h
include/configs/hammerhead.h
include/configs/mimc200.h
Diffstat (limited to 'include/asm-ppc/4xx_pcie.h')
| -rw-r--r-- | include/asm-ppc/4xx_pcie.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h index a7cf1e8..a0e88de 100644 --- a/include/asm-ppc/4xx_pcie.h +++ b/include/asm-ppc/4xx_pcie.h @@ -18,9 +18,9 @@ #define DCRN_SDR0_CFGDATA 0x00f #if defined(CONFIG_440SPE) -#define CFG_PCIE_NR_PORTS 3 +#define CONFIG_SYS_PCIE_NR_PORTS 3 -#define CFG_PCIE_ADDR_HIGH 0x0000000d +#define CONFIG_SYS_PCIE_ADDR_HIGH 0x0000000d #define DCRN_PCIE0_BASE 0x100 #define DCRN_PCIE1_BASE 0x120 @@ -32,9 +32,9 @@ #endif #if defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define CFG_PCIE_NR_PORTS 2 +#define CONFIG_SYS_PCIE_NR_PORTS 2 -#define CFG_PCIE_ADDR_HIGH 0x0000000d +#define CONFIG_SYS_PCIE_ADDR_HIGH 0x0000000d #define DCRN_PCIE0_BASE 0x100 #define DCRN_PCIE1_BASE 0x120 @@ -44,9 +44,9 @@ #endif #if defined(CONFIG_405EX) -#define CFG_PCIE_NR_PORTS 2 +#define CONFIG_SYS_PCIE_NR_PORTS 2 -#define CFG_PCIE_ADDR_HIGH 0x00000000 +#define CONFIG_SYS_PCIE_ADDR_HIGH 0x00000000 #define DCRN_PCIE0_BASE 0x040 #define DCRN_PCIE1_BASE 0x060 @@ -406,7 +406,7 @@ static inline u32 sdr_base(int port) return PCIE0_SDR; case 1: return PCIE1_SDR; -#if CFG_PCIE_NR_PORTS > 2 +#if CONFIG_SYS_PCIE_NR_PORTS > 2 case 2: return PCIE2_SDR; #endif |