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authorwdenk <wdenk>2003-10-09 20:09:04 +0000
committerwdenk <wdenk>2003-10-09 20:09:04 +0000
commit5da627a424b3ad2d38a81886ba4a18e5123a6788 (patch)
tree13d274effe8b9c740a07f4cb47989f3215c20bb4 /include/asm-mips/mipsregs.h
parent15647dc7fd86bbaeb68740929ecb9f8473c7ceae (diff)
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* Patch by Steven Scholz, 10 Oct 2003
- Add support for Altera FPGA ACEX1K * Patches by Thomas Lange, 09 Oct 2003: - Endian swap ATA identity for all big endian CPUs, not just PPC - MIPS only: New option CONFIG_MEMSIZE_IN_BYTES for passing memsize args to linux - add support for dbau1x00 board (MIPS32)
Diffstat (limited to 'include/asm-mips/mipsregs.h')
-rw-r--r--include/asm-mips/mipsregs.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 3100738..0586c53 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -8,6 +8,7 @@
* Modified for further R[236]000 support by Paul M. Antoine, 1996.
* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
+ * Copyright (C) 2003 Maciej W. Rozycki
*/
#ifndef _ASM_MIPSREGS_H
#define _ASM_MIPSREGS_H
@@ -239,6 +240,12 @@
:"=r" (__res)); \
__res;})
+#define tlb_write_indexed() \
+ __asm__ __volatile__( \
+ ".set noreorder\n\t" \
+ "tlbwi\n\t" \
+".set reorder")
+
/*
* R4x00 interrupt enable / cause bits
*/