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| author | wdenk <wdenk> | 2003-02-28 00:49:47 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2003-02-28 00:49:47 +0000 |
| commit | 6069ff265362ef6239749b5f598b137f407b821e (patch) | |
| tree | 991432052f2aa7da45d8c1d51db9f80478d7e75d /include/asm-mips/cacheops.h | |
| parent | 2a9e02ead3024f33658f1f4110834d0601dd6b2f (diff) | |
| download | u-boot-imx-6069ff265362ef6239749b5f598b137f407b821e.zip u-boot-imx-6069ff265362ef6239749b5f598b137f407b821e.tar.gz u-boot-imx-6069ff265362ef6239749b5f598b137f407b821e.tar.bz2 | |
* Add support for 16 MB flash configuration of TRAB board
* Patch by Erwin Rol, 27 Feb 2003:
Add support for RTEMS
* Add image information to README
* Fix dual PCMCIA slot support (when running with just one
slot populated)
* Add VFD type detection to trab board
* extend drivers/cs8900.c driver to synchronize ethaddr environment
variable with value in the EEPROM
* Start adding MIPS support files
Diffstat (limited to 'include/asm-mips/cacheops.h')
| -rw-r--r-- | include/asm-mips/cacheops.h | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h new file mode 100644 index 0000000..66b0b36 --- /dev/null +++ b/include/asm-mips/cacheops.h @@ -0,0 +1,47 @@ +/* + * Cache operations for the cache instruction. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * (C) Copyright 1996, 1997 by Ralf Baechle + */ +#ifndef __ASM_MIPS_CACHEOPS_H +#define __ASM_MIPS_CACHEOPS_H + +/* + * Cache Operations + */ +#define Index_Invalidate_I 0x00 +#define Index_Writeback_Inv_D 0x01 +#define Index_Invalidate_SI 0x02 +#define Index_Writeback_Inv_SD 0x03 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 +#define Index_Store_Tag_SI 0x0A +#define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_D 0x0d +#define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_I 0x10 +#define Hit_Invalidate_D 0x11 +#define Hit_Invalidate_SI 0x12 +#define Hit_Invalidate_SD 0x13 +#define Fill 0x14 +#define Hit_Writeback_Inv_D 0x15 + /* 0x16 is unused */ +#define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 + /* 0x1a is unused */ +#define Hit_Writeback_SD 0x1b + /* 0x1c is unused */ + /* 0x1e is unused */ +#define Hit_Set_Virtual_SI 0x1e +#define Hit_Set_Virtual_SD 0x1f + +#endif /* __ASM_MIPS_CACHEOPS_H */ |