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| author | Dave Liu <daveliu@freescale.com> | 2008-11-21 16:31:35 +0800 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2009-01-23 17:03:14 -0600 |
| commit | 22cca7e1cd54590e967c73558b07ffbdccd39504 (patch) | |
| tree | 4f6322f49d1eef36f8af7e5e19297f1699e5b9a4 /include/asm-mips/cachectl.h | |
| parent | 22ff3d01348e0a2dc369b7efcbac30e4ce86d178 (diff) | |
| download | u-boot-imx-22cca7e1cd54590e967c73558b07ffbdccd39504.zip u-boot-imx-22cca7e1cd54590e967c73558b07ffbdccd39504.tar.gz u-boot-imx-22cca7e1cd54590e967c73558b07ffbdccd39504.tar.bz2 | |
fsl-ddr: make the self refresh idle threshold configurable
Some 85xx processors have the advanced power management feature,
such as wake up ARP, that needs enable the automatic self refresh.
If the DDR controller pass the SR_IT (self refresh idle threshold)
idle cycles, it will automatically enter self refresh. However,
anytime one transaction is issued to the DDR controller, it will
reset the counter and exit self refresh state.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'include/asm-mips/cachectl.h')
0 files changed, 0 insertions, 0 deletions