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| author | Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> | 2008-03-25 11:43:17 +0900 |
|---|---|---|
| committer | Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> | 2008-03-25 11:43:17 +0900 |
| commit | 282223a607c611425fa33f5428f8eae6636972bb (patch) | |
| tree | 00e55757868b01a1aa7853fdcd9f683a0f631a77 /include/asm-mips/byteorder.h | |
| parent | e1390801a3c1a2b6d12fa90be368efc19f5b9bfd (diff) | |
| download | u-boot-imx-282223a607c611425fa33f5428f8eae6636972bb.zip u-boot-imx-282223a607c611425fa33f5428f8eae6636972bb.tar.gz u-boot-imx-282223a607c611425fa33f5428f8eae6636972bb.tar.bz2 | |
[MIPS] asm headers' updates
Make some asm headers adjusted to the latest Linux kernel.
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Diffstat (limited to 'include/asm-mips/byteorder.h')
| -rw-r--r-- | include/asm-mips/byteorder.h | 60 |
1 files changed, 52 insertions, 8 deletions
diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h index b9604cf..b5e685f 100644 --- a/include/asm-mips/byteorder.h +++ b/include/asm-mips/byteorder.h @@ -1,18 +1,62 @@ -/* $Id: byteorder.h,v 1.8 1998/11/02 09:29:32 ralf Exp $ - * +/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) by Ralf Baechle + * Copyright (C) 1996, 99, 2003 by Ralf Baechle */ -#ifndef _MIPS_BYTEORDER_H -#define _MIPS_BYTEORDER_H +#ifndef _ASM_BYTEORDER_H +#define _ASM_BYTEORDER_H #include <asm/types.h> #ifdef __GNUC__ +#ifdef CONFIG_CPU_MIPSR2 + +static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) +{ + __asm__( + " wsbh %0, %1 \n" + : "=r" (x) + : "r" (x)); + + return x; +} +#define __arch__swab16(x) ___arch__swab16(x) + +static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) +{ + __asm__( + " wsbh %0, %1 \n" + " rotr %0, %0, 16 \n" + : "=r" (x) + : "r" (x)); + + return x; +} +#define __arch__swab32(x) ___arch__swab32(x) + +#ifdef CONFIG_CPU_MIPS64_R2 + +static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x) +{ + __asm__( + " dsbh %0, %1 \n" + " dshd %0, %0 \n" + " drotr %0, %0, 32 \n" + : "=r" (x) + : "r" (x)); + + return x; +} + +#define __arch__swab64(x) ___arch__swab64(x) + +#endif /* CONFIG_CPU_MIPS64_R2 */ + +#endif /* CONFIG_CPU_MIPSR2 */ + #if !defined(__STRICT_ANSI__) || defined(__KERNEL__) # define __BYTEORDER_HAS_U64__ # define __SWAB_64_THRU_32__ @@ -20,12 +64,12 @@ #endif /* __GNUC__ */ -#if defined (__MIPSEB__) +#if defined(__MIPSEB__) # include <linux/byteorder/big_endian.h> -#elif defined (__MIPSEL__) +#elif defined(__MIPSEL__) # include <linux/byteorder/little_endian.h> #else # error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" #endif -#endif /* _MIPS_BYTEORDER_H */ +#endif /* _ASM_BYTEORDER_H */ |