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authorTsiChungLiew <Tsi-Chung.Liew@freescale.com>2008-01-14 17:11:47 -0600
committerTsiChungLiew <Tsi-Chung.Liew@freescale.com>2008-01-17 14:59:40 -0600
commit2e72ad0644b940817a89a3590ce0d7b99c05c396 (patch)
treeb0079811d0ec53b50823fd5f144f6965fd38c883 /include/asm-m68k
parentd2b16493480ac3d4a60ad7d835b0dc27d2e99cee (diff)
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ColdFire: PCI and misc updates for MCF5445x
Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> Signed-off by: John Rigby <jrigby@freescale.com>
Diffstat (limited to 'include/asm-m68k')
-rw-r--r--include/asm-m68k/immap.h8
-rw-r--r--include/asm-m68k/m5445x.h14
2 files changed, 11 insertions, 11 deletions
diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h
index ffb9a37..912753d 100644
--- a/include/asm-m68k/immap.h
+++ b/include/asm-m68k/immap.h
@@ -232,10 +232,10 @@
#define CFG_NUM_IRQS (128)
#ifdef CONFIG_PCI
-#define CFG_PCI_BAR0 CFG_SDRAM_BASE
-#define CFG_PCI_BAR4 CFG_SDRAM_BASE
-#define CFG_PCI_TBATR0 (CFG_SDRAM_BASE)
-#define CFG_PCI_TBATR4 (CFG_SDRAM_BASE)
+#define CFG_PCI_BAR0 (CFG_MBAR)
+#define CFG_PCI_BAR5 (CFG_SDRAM_BASE)
+#define CFG_PCI_TBATR0 (CFG_MBAR)
+#define CFG_PCI_TBATR5 (CFG_SDRAM_BASE)
#endif
#endif /* CONFIG_M54455 */
diff --git a/include/asm-m68k/m5445x.h b/include/asm-m68k/m5445x.h
index f3bd229..7fcf4ef 100644
--- a/include/asm-m68k/m5445x.h
+++ b/include/asm-m68k/m5445x.h
@@ -1204,13 +1204,13 @@
#define PCI_TCR1_P (0x00010000) /* Prefetch reads */
#define PCI_TCR1_WCD (0x00000100) /* Write combine disable */
-#define PCI_TCR1_B5E (0x00002000) /* */
-#define PCI_TCR1_B4E (0x00001000) /* */
-#define PCI_TCR1_B3E (0x00000800) /* */
-#define PCI_TCR1_B2E (0x00000400) /* */
-#define PCI_TCR1_B1E (0x00000200) /* */
-#define PCI_TCR1_B0E (0x00000100) /* */
-#define PCI_TCR1_CR (0x00000001) /* */
+#define PCI_TCR2_B5E (0x00002000) /* */
+#define PCI_TCR2_B4E (0x00001000) /* */
+#define PCI_TCR2_B3E (0x00000800) /* */
+#define PCI_TCR2_B2E (0x00000400) /* */
+#define PCI_TCR2_B1E (0x00000200) /* */
+#define PCI_TCR2_B0E (0x00000100) /* */
+#define PCI_TCR2_CR (0x00000001) /* */
#define PCI_TBATR_BAT(x) ((x & 0xFFF) << 20)
#define PCI_TBATR_EN (0x00000001) /* Enable */