Merge branch 'master' of git://git.denx.de/u-boot-coldfire

1 files changed, 0 insertions, 347 deletions

diff --git a/include/asm-m68k/m5329.h b/include/asm-m68k/m5329.h
index c1669dc..c7ebed1 100644
--- a/include/asm-m68k/m5329.h
+++ b/include/asm-m68k/m5329.h
@@ -187,65 +187,6 @@
 #define CFATR_TYPE			(0x01)
 
 /*********************************************************************
-* FlexBus Chip Selects (FBCS)
-*********************************************************************/
-/* Bit definitions and macros for FBCS_CSAR */
-#define CSAR_BA(x)			(((x)&0xFFFF)<<16)
-
-/* Bit definitions and macros for FBCS_CSMR */
-#define CSMR_BAM(x)			(((x)&0xFFFF)<<16)
-#define CSMR_BAM_4G			(0xFFFF0000)
-#define CSMR_BAM_2G			(0x7FFF0000)
-#define CSMR_BAM_1G			(0x3FFF0000)
-#define CSMR_BAM_1024M			(0x3FFF0000)
-#define CSMR_BAM_512M			(0x1FFF0000)
-#define CSMR_BAM_256M			(0x0FFF0000)
-#define CSMR_BAM_128M			(0x07FF0000)
-#define CSMR_BAM_64M			(0x03FF0000)
-#define CSMR_BAM_32M			(0x01FF0000)
-#define CSMR_BAM_16M			(0x00FF0000)
-#define CSMR_BAM_8M			(0x007F0000)
-#define CSMR_BAM_4M			(0x003F0000)
-#define CSMR_BAM_2M			(0x001F0000)
-#define CSMR_BAM_1M			(0x000F0000)
-#define CSMR_BAM_1024K			(0x000F0000)
-#define CSMR_BAM_512K			(0x00070000)
-#define CSMR_BAM_256K			(0x00030000)
-#define CSMR_BAM_128K			(0x00010000)
-#define CSMR_BAM_64K			(0x00000000)
-#define CSMR_WP				(0x00000100)
-#define CSMR_V				(0x00000001)
-
-/* Bit definitions and macros for FBCS_CSCR */
-#define CSCR_SWS(x)			(((x)&0x3F)<<26)
-#define CSCR_ASET(x)			(((x)&0x03)<<20)
-#define CSCR_SWSEN			(0x00800000)
-#define CSCR_ASET_4CLK			(0x00300000)
-#define CSCR_ASET_3CLK			(0x00200000)
-#define CSCR_ASET_2CLK			(0x00100000)
-#define CSCR_ASET_1CLK			(0x00000000)
-#define CSCR_RDAH(x)			(((x)&0x03)<<18)
-#define CSCR_RDAH_4CYC			(0x000C0000)
-#define CSCR_RDAH_3CYC			(0x00080000)
-#define CSCR_RDAH_2CYC			(0x00040000)
-#define CSCR_RDAH_1CYC			(0x00000000)
-#define CSCR_WRAH(x)			(((x)&0x03)<<16)
-#define CSCR_WDAH_4CYC			(0x00003000)
-#define CSCR_WDAH_3CYC			(0x00002000)
-#define CSCR_WDAH_2CYC			(0x00001000)
-#define CSCR_WDAH_1CYC			(0x00000000)
-#define CSCR_WS(x)			(((x)&0x3F)<<10)
-#define CSCR_SBM			(0x00000200)
-#define CSCR_AA				(0x00000100)
-#define CSCR_PS_MASK			(0x000000C0)
-#define CSCR_PS_32			(0x00000000)
-#define CSCR_PS_16			(0x00000080)
-#define CSCR_PS_8			(0x00000040)
-#define CSCR_BEM			(0x00000020)
-#define CSCR_BSTR			(0x00000010)
-#define CSCR_BSTW			(0x00000008)
-
-/*********************************************************************
 * Reset Controller Module (RCM)
 *********************************************************************/
 
@@ -261,100 +202,6 @@
 #define RCM_RSR_SOFT			(0x20)
 
 /*********************************************************************
-* FlexCAN Module (CAN)
-*********************************************************************/
-/* Bit definitions and macros for CAN_CANMCR */
-#define CANMCR_MDIS			(0x80000000)
-#define CANMCR_FRZ			(0x40000000)
-#define CANMCR_HALT			(0x10000000)
-#define CANMCR_NORDY			(0x08000000)
-#define CANMCR_SOFTRST			(0x02000000)
-#define CANMCR_FRZACK			(0x01000000)
-#define CANMCR_SUPV			(0x00800000)
-#define CANMCR_LPMACK			(0x00100000)
-#define CANMCR_MAXMB(x)			(((x)&0x0F))
-
-/* Bit definitions and macros for CAN_CANCTRL */
-#define CANCTRL_PRESDIV(x)		(((x)&0xFF)<<24)
-#define CANCTRL_RJW(x)			(((x)&0x03)<<22)
-#define CANCTRL_PSEG1(x)		(((x)&0x07)<<19)
-#define CANCTRL_PSEG2(x)		(((x)&0x07)<<16)
-#define CANCTRL_BOFFMSK			(0x00008000)
-#define CANCTRL_ERRMSK			(0x00004000)
-#define CANCTRL_CLKSRC			(0x00002000)
-#define CANCTRL_LPB			(0x00001000)
-#define CANCTRL_SMP			(0x00000080)
-#define CANCTRL_BOFFREC			(0x00000040)
-#define CANCTRL_TSYNC			(0x00000020)
-#define CANCTRL_LBUF			(0x00000010)
-#define CANCTRL_LOM			(0x00000008)
-#define CANCTRL_PROPSEG(x)		(((x)&0x07))
-
-/* Bit definitions and macros for CAN_TIMER */
-#define TIMER_TIMER(x)			((x)&0xFFFF)
-
-/* Bit definitions and macros for CAN_RXGMASK */
-#define RXGMASK_MI(x)			((x)&0x1FFFFFFF)
-
-/* Bit definitions and macros for CAN_ERRCNT */
-#define ERRCNT_TXECTR(x)		(((x)&0xFF))
-#define ERRCNT_RXECTR(x)		(((x)&0xFF)<<8)
-
-/* Bit definitions and macros for CAN_ERRSTAT */
-#define ERRSTAT_BITERR1			(0x00008000)
-#define ERRSTAT_BITERR0			(0x00004000)
-#define ERRSTAT_ACKERR			(0x00002000)
-#define ERRSTAT_CRCERR			(0x00001000)
-#define ERRSTAT_FRMERR			(0x00000800)
-#define ERRSTAT_STFERR			(0x00000400)
-#define ERRSTAT_TXWRN			(0x00000200)
-#define ERRSTAT_RXWRN			(0x00000100)
-#define ERRSTAT_IDLE			(0x00000080)
-#define ERRSTAT_TXRX			(0x00000040)
-#define ERRSTAT_FLT_BUSOFF		(0x00000020)
-#define ERRSTAT_FLT_PASSIVE		(0x00000010)
-#define ERRSTAT_FLT_ACTIVE		(0x00000000)
-#define ERRSTAT_BOFFINT			(0x00000004)
-#define ERRSTAT_ERRINT			(0x00000002)
-#define ERRSTAT_WAKINT			(0x00000001)
-
-/* Bit definitions and macros for CAN_IMASK */
-#define IMASK_BUF15M			(0x00008000)
-#define IMASK_BUF14M			(0x00004000)
-#define IMASK_BUF13M			(0x00002000)
-#define IMASK_BUF12M			(0x00001000)
-#define IMASK_BUF11M			(0x00000800)
-#define IMASK_BUF10M			(0x00000400)
-#define IMASK_BUF9M			(0x00000200)
-#define IMASK_BUF8M			(0x00000100)
-#define IMASK_BUF7M			(0x00000080)
-#define IMASK_BUF6M			(0x00000040)
-#define IMASK_BUF5M			(0x00000020)
-#define IMASK_BUF4M			(0x00000010)
-#define IMASK_BUF3M			(0x00000008)
-#define IMASK_BUF2M			(0x00000004)
-#define IMASK_BUF1M			(0x00000002)
-#define IMASK_BUF0M			(0x00000001)
-
-/* Bit definitions and macros for CAN_IFLAG */
-#define IFLAG_BUF15I			(0x00008000)
-#define IFLAG_BUF14I			(0x00004000)
-#define IFLAG_BUF13I			(0x00002000)
-#define IFLAG_BUF12I			(0x00001000)
-#define IFLAG_BUF11I			(0x00000800)
-#define IFLAG_BUF10I			(0x00000400)
-#define IFLAG_BUF9I			(0x00000200)
-#define IFLAG_BUF8I			(0x00000100)
-#define IFLAG_BUF7I			(0x00000080)
-#define IFLAG_BUF6I			(0x00000040)
-#define IFLAG_BUF5I			(0x00000020)
-#define IFLAG_BUF4I			(0x00000010)
-#define IFLAG_BUF3I			(0x00000008)
-#define IFLAG_BUF2I			(0x00000004)
-#define IFLAG_BUF1I			(0x00000002)
-#define IFLAG_BUF0I			(0x00000001)
-
-/*********************************************************************
 * Interrupt Controller (INTC)
 *********************************************************************/
 #define INTC0_EPORT			INTC_IPRL_INT1
@@ -411,200 +258,6 @@
 /* 49 - 61 Reserved */
 #define INT0_HI_SCM			(62)
 
-/* Bit definitions and macros for INTC_IPRH */
-#define INTC_IPRH_INT63			(0x80000000)
-#define INTC_IPRH_INT62			(0x40000000)
-#define INTC_IPRH_INT61			(0x20000000)
-#define INTC_IPRH_INT60			(0x10000000)
-#define INTC_IPRH_INT59			(0x08000000)
-#define INTC_IPRH_INT58			(0x04000000)
-#define INTC_IPRH_INT57			(0x02000000)
-#define INTC_IPRH_INT56			(0x01000000)
-#define INTC_IPRH_INT55			(0x00800000)
-#define INTC_IPRH_INT54			(0x00400000)
-#define INTC_IPRH_INT53			(0x00200000)
-#define INTC_IPRH_INT52			(0x00100000)
-#define INTC_IPRH_INT51			(0x00080000)
-#define INTC_IPRH_INT50			(0x00040000)
-#define INTC_IPRH_INT49			(0x00020000)
-#define INTC_IPRH_INT48			(0x00010000)
-#define INTC_IPRH_INT47			(0x00008000)
-#define INTC_IPRH_INT46			(0x00004000)
-#define INTC_IPRH_INT45			(0x00002000)
-#define INTC_IPRH_INT44			(0x00001000)
-#define INTC_IPRH_INT43			(0x00000800)
-#define INTC_IPRH_INT42			(0x00000400)
-#define INTC_IPRH_INT41			(0x00000200)
-#define INTC_IPRH_INT40			(0x00000100)
-#define INTC_IPRH_INT39			(0x00000080)
-#define INTC_IPRH_INT38			(0x00000040)
-#define INTC_IPRH_INT37			(0x00000020)
-#define INTC_IPRH_INT36			(0x00000010)
-#define INTC_IPRH_INT35			(0x00000008)
-#define INTC_IPRH_INT34			(0x00000004)
-#define INTC_IPRH_INT33			(0x00000002)
-#define INTC_IPRH_INT32			(0x00000001)
-
-/* Bit definitions and macros for INTC_IPRL */
-#define INTC_IPRL_INT31			(0x80000000)
-#define INTC_IPRL_INT30			(0x40000000)
-#define INTC_IPRL_INT29			(0x20000000)
-#define INTC_IPRL_INT28			(0x10000000)
-#define INTC_IPRL_INT27			(0x08000000)
-#define INTC_IPRL_INT26			(0x04000000)
-#define INTC_IPRL_INT25			(0x02000000)
-#define INTC_IPRL_INT24			(0x01000000)
-#define INTC_IPRL_INT23			(0x00800000)
-#define INTC_IPRL_INT22			(0x00400000)
-#define INTC_IPRL_INT21			(0x00200000)
-#define INTC_IPRL_INT20			(0x00100000)
-#define INTC_IPRL_INT19			(0x00080000)
-#define INTC_IPRL_INT18			(0x00040000)
-#define INTC_IPRL_INT17			(0x00020000)
-#define INTC_IPRL_INT16			(0x00010000)
-#define INTC_IPRL_INT15			(0x00008000)
-#define INTC_IPRL_INT14			(0x00004000)
-#define INTC_IPRL_INT13			(0x00002000)
-#define INTC_IPRL_INT12			(0x00001000)
-#define INTC_IPRL_INT11			(0x00000800)
-#define INTC_IPRL_INT10			(0x00000400)
-#define INTC_IPRL_INT9			(0x00000200)
-#define INTC_IPRL_INT8			(0x00000100)
-#define INTC_IPRL_INT7			(0x00000080)
-#define INTC_IPRL_INT6			(0x00000040)
-#define INTC_IPRL_INT5			(0x00000020)
-#define INTC_IPRL_INT4			(0x00000010)
-#define INTC_IPRL_INT3			(0x00000008)
-#define INTC_IPRL_INT2			(0x00000004)
-#define INTC_IPRL_INT1			(0x00000002)
-#define INTC_IPRL_INT0			(0x00000001)
-
-/* Bit definitions and macros for INTC_ICONFIG */
-#define INTC_ICFG_ELVLPRI7		(0x8000)
-#define INTC_ICFG_ELVLPRI6		(0x4000)
-#define INTC_ICFG_ELVLPRI5		(0x2000)
-#define INTC_ICFG_ELVLPRI4		(0x1000)
-#define INTC_ICFG_ELVLPRI3		(0x0800)
-#define INTC_ICFG_ELVLPRI2		(0x0400)
-#define INTC_ICFG_ELVLPRI1		(0x0200)
-#define INTC_ICFG_EMASK			(0x0020)
-
-/* Bit definitions and macros for INTC_SIMR */
-#define INTC_SIMR_SALL			(0x40)
-#define INTC_SIMR_SIMR(x)		((x)&0x3F)
-
-/* Bit definitions and macros for INTC_CIMR */
-#define INTC_CIMR_CALL			(0x40)
-#define INTC_CIMR_CIMR(x)		((x)&0x3F)
-
-/* Bit definitions and macros for INTC_CLMASK */
-#define INTC_CLMASK_CLMASK(x)		((x)&0x0F)
-
-/* Bit definitions and macros for INTC_SLMASK */
-#define INTC_SLMASK_SLMASK(x)		((x)&0x0F)
-
-/* Bit definitions and macros for INTC_ICR */
-#define INTC_ICR_IL(x)			((x)&0x07)
-
-/*********************************************************************
-* Queued Serial Peripheral Interface (QSPI)
-*********************************************************************/
-/* Bit definitions and macros for QSPI_QMR */
-#define QSPI_QMR_MSTR			(0x8000)
-#define QSPI_QMR_DOHIE			(0x4000)
-#define QSPI_QMR_BITS(x)		(((x)&0x000F)<<10)
-#define QSPI_QMR_CPOL			(0x0200)
-#define QSPI_QMR_CPHA			(0x0100)
-#define QSPI_QMR_BAUD(x)		((x)&0x00FF)
-
-/* Bit definitions and macros for QSPI_QDLYR */
-#define QSPI_QDLYR_SPE			(0x8000)
-#define QSPI_QDLYR_QCD(x)		(((x)&0x007F)<<8)
-#define QSPI_QDLYR_DTL(x)		((x)&0x00FF)
-
-/* Bit definitions and macros for QSPI_QWR */
-#define QSPI_QWR_NEWQP(x)		((x)&0x000F)
-#define QSPI_QWR_ENDQP(x)		(((x)&0x000F)<<8)
-#define QSPI_QWR_CSIV			(0x1000)
-#define QSPI_QWR_WRTO			(0x2000)
-#define QSPI_QWR_WREN			(0x4000)
-#define QSPI_QWR_HALT			(0x8000)
-
-/* Bit definitions and macros for QSPI_QIR */
-#define QSPI_QIR_WCEFB			(0x8000)
-#define QSPI_QIR_ABRTB			(0x4000)
-#define QSPI_QIR_ABRTL			(0x1000)
-#define QSPI_QIR_WCEFE			(0x0800)
-#define QSPI_QIR_ABRTE			(0x0400)
-#define QSPI_QIR_SPIFE			(0x0100)
-#define QSPI_QIR_WCEF			(0x0008)
-#define QSPI_QIR_ABRT			(0x0004)
-#define QSPI_QIR_SPIF			(0x0001)
-
-/* Bit definitions and macros for QSPI_QAR */
-#define QSPI_QAR_ADDR(x)		((x)&0x003F)
-#define QSPI_QAR_TRANS			(0x0000)
-#define QSPI_QAR_RECV			(0x0010)
-#define QSPI_QAR_CMD			(0x0020)
-
-/* Bit definitions and macros for QSPI_QDR */
-#define QSPI_QDR_CONT			(0x8000)
-#define QSPI_QDR_BITSE			(0x4000)
-#define QSPI_QDR_DT			(0x2000)
-#define QSPI_QDR_DSCK			(0x1000)
-#define QSPI_QDR_QSPI_CS3		(0x0800)
-#define QSPI_QDR_QSPI_CS2		(0x0400)
-#define QSPI_QDR_QSPI_CS1		(0x0200)
-#define QSPI_QDR_QSPI_CS0		(0x0100)
-
-/*********************************************************************
-* Pulse Width Modulation (PWM)
-*********************************************************************/
-/* Bit definitions and macros for PWM_E */
-#define PWM_EN_PWME7			(0x80)
-#define PWM_EN_PWME5			(0x20)
-#define PWM_EN_PWME3			(0x08)
-#define PWM_EN_PWME1			(0x02)
-
-/* Bit definitions and macros for PWM_POL */
-#define PWM_POL_PPOL7			(0x80)
-#define PWM_POL_PPOL5			(0x20)
-#define PWM_POL_PPOL3			(0x08)
-#define PWM_POL_PPOL1			(0x02)
-
-/* Bit definitions and macros for PWM_CLK */
-#define PWM_CLK_PCLK7			(0x80)
-#define PWM_CLK_PCLK5			(0x20)
-#define PWM_CLK_PCLK3			(0x08)
-#define PWM_CLK_PCLK1			(0x02)
-
-/* Bit definitions and macros for PWM_PRCLK */
-#define PWM_PRCLK_PCKB(x)		(((x)&0x07)<<4)
-#define PWM_PRCLK_PCKA(x)		((x)&0x07)
-
-/* Bit definitions and macros for PWM_CAE */
-#define PWM_CAE_CAE7			(0x80)
-#define PWM_CAE_CAE5			(0x20)
-#define PWM_CAE_CAE3			(0x08)
-#define PWM_CAE_CAE1			(0x02)
-
-/* Bit definitions and macros for PWM_CTL */
-#define PWM_CTL_CON67			(0x80)
-#define PWM_CTL_CON45			(0x40)
-#define PWM_CTL_CON23			(0x20)
-#define PWM_CTL_CON01			(0x10)
-#define PWM_CTL_PSWAR			(0x08)
-#define PWM_CTL_PFRZ			(0x04)
-
-/* Bit definitions and macros for PWM_SDN */
-#define PWM_SDN_IF			(0x80)
-#define PWM_SDN_IE			(0x40)
-#define PWM_SDN_RESTART			(0x20)
-#define PWM_SDN_LVL			(0x10)
-#define PWM_SDN_PWM7IN			(0x04)
-#define PWM_SDN_PWM7IL			(0x02)
-#define PWM_SDN_SDNEN			(0x01)
-
 /*********************************************************************
 * Watchdog Timer Modules (WTM)
 *********************************************************************/