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authorTsiChung Liew <Tsi-Chung.Liew@freescale.com>2008-10-21 10:03:07 +0000
committerJohn Rigby <jrigby@freescale.com>2008-11-03 09:45:58 -0700
commit012522fef3b382469125beb46a315ab4dee02fb0 (patch)
tree9bc6b0cc47ec08dd3efb07a75eaa50fd04ec5f32 /include/asm-m68k/m5275.h
parentac2331aee99ad36be0fcfed8c49922e3c61b576d (diff)
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ColdFire: Modules header files cleanup
Consolidate ATA, ePORT, QSPI, FlexCan, PWM, RNG, MDHA, SKHA, INTC, and FlexBus structures and definitions in immap_5xxx.h to more unify modules header files. Append DSPI support for m547x_8x. SSI cleanup. Remove USB Host structure from immap_539.h. Apply changes to use FlexBus structures in mcf52x2's cpu_init.c and platform configuration files. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Diffstat (limited to 'include/asm-m68k/m5275.h')
-rw-r--r--include/asm-m68k/m5275.h46
1 files changed, 0 insertions, 46 deletions
diff --git a/include/asm-m68k/m5275.h b/include/asm-m68k/m5275.h
index 89c6c92..24dbae2 100644
--- a/include/asm-m68k/m5275.h
+++ b/include/asm-m68k/m5275.h
@@ -30,18 +30,6 @@
* Define the 5275 SIM register set addresses. These are similar,
* but not quite identical to the 5282 registers and offsets.
*/
-#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
-#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */
-#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
-#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
-#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
-#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
-#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
-#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
-#define MCFINTC_IRLR 0x18 /* */
-#define MCFINTC_IACKL 0x19 /* */
-#define MCFINTC_ICR0 0x40 /* Base ICR register */
-
#define MCF_GPIO_PAR_UART 0x10007c
#define UART0_ENABLE_MASK 0x000f
#define UART1_ENABLE_MASK 0x00f0
@@ -198,40 +186,6 @@
#define INT1_HI_FEC1_BABR (35)
/* 36-63 Reserved */
-/* Bit definitions and macros for INTC_IPRL */
-#define INTC_IPRL_INT31 (0x80000000)
-#define INTC_IPRL_INT30 (0x40000000)
-#define INTC_IPRL_INT29 (0x20000000)
-#define INTC_IPRL_INT28 (0x10000000)
-#define INTC_IPRL_INT27 (0x08000000)
-#define INTC_IPRL_INT26 (0x04000000)
-#define INTC_IPRL_INT25 (0x02000000)
-#define INTC_IPRL_INT24 (0x01000000)
-#define INTC_IPRL_INT23 (0x00800000)
-#define INTC_IPRL_INT22 (0x00400000)
-#define INTC_IPRL_INT21 (0x00200000)
-#define INTC_IPRL_INT20 (0x00100000)
-#define INTC_IPRL_INT19 (0x00080000)
-#define INTC_IPRL_INT18 (0x00040000)
-#define INTC_IPRL_INT17 (0x00020000)
-#define INTC_IPRL_INT16 (0x00010000)
-#define INTC_IPRL_INT15 (0x00008000)
-#define INTC_IPRL_INT14 (0x00004000)
-#define INTC_IPRL_INT13 (0x00002000)
-#define INTC_IPRL_INT12 (0x00001000)
-#define INTC_IPRL_INT11 (0x00000800)
-#define INTC_IPRL_INT10 (0x00000400)
-#define INTC_IPRL_INT9 (0x00000200)
-#define INTC_IPRL_INT8 (0x00000100)
-#define INTC_IPRL_INT7 (0x00000080)
-#define INTC_IPRL_INT6 (0x00000040)
-#define INTC_IPRL_INT5 (0x00000020)
-#define INTC_IPRL_INT4 (0x00000010)
-#define INTC_IPRL_INT3 (0x00000008)
-#define INTC_IPRL_INT2 (0x00000004)
-#define INTC_IPRL_INT1 (0x00000002)
-#define INTC_IPRL_INT0 (0x00000001)
-
/* Bit definitions and macros for RCR */
#define RCM_RCR_FRCRSTOUT (0x40)
#define RCM_RCR_SOFTRST (0x80)