ColdFire: Correct bit definition

Use correct definition for _MASK and _UNMASK. It was combined in
the previous used and causes confusion.

Signed-off-by: TsiChung Liew <tsicliew@gmail.com>

1 files changed, 53 insertions, 55 deletions

diff --git a/include/asm-m68k/m5227x.h b/include/asm-m68k/m5227x.h
index 824d333..c77d5dd 100644
--- a/include/asm-m68k/m5227x.h
+++ b/include/asm-m68k/m5227x.h
@@ -117,36 +117,34 @@
 
 /* Bit definitions and macros for CCR */
 #define CCM_CCR_DRAMSEL			(0x0100)
-#define CCM_CCR_CSC_MASK		(0xFF3F)
+#define CCM_CCR_CSC_UNMASK		(0xFF3F)
 #define CCM_CCR_CSC_FBCS5_CS4		(0x00C0)
 #define CCM_CCR_CSC_FBCS5_A22		(0x0080)
 #define CCM_CCR_CSC_FB_A23_A22		(0x0040)
 #define CCM_CCR_LIMP			(0x0020)
 #define CCM_CCR_LOAD			(0x0010)
-#define CCM_CCR_BOOTPS_MASK		(0xFFF3)
+#define CCM_CCR_BOOTPS_UNMASK		(0xFFF3)
 #define CCM_CCR_BOOTPS_PS16		(0x0008)
 #define CCM_CCR_BOOTPS_PS8		(0x0004)
 #define CCM_CCR_BOOTPS_PS32		(0x0000)
 #define CCM_CCR_OSCMODE_OSCBYPASS	(0x0002)
 
 /* Bit definitions and macros for RCON */
-#define CCM_RCON_CSC_MASK		(0xFF3F)
+#define CCM_RCON_CSC_UNMASK		(0xFF3F)
 #define CCM_RCON_CSC_FBCS5_CS4		(0x00C0)
 #define CCM_RCON_CSC_FBCS5_A22		(0x0080)
 #define CCM_RCON_CSC_FB_A23_A22		(0x0040)
 #define CCM_RCON_LIMP			(0x0020)
 #define CCM_RCON_LOAD			(0x0010)
-#define CCM_RCON_BOOTPS_MASK		(0xFFF3)
+#define CCM_RCON_BOOTPS_UNMASK		(0xFFF3)
 #define CCM_RCON_BOOTPS_PS16		(0x0008)
 #define CCM_RCON_BOOTPS_PS8		(0x0004)
 #define CCM_RCON_BOOTPS_PS32		(0x0000)
 #define CCM_RCON_OSCMODE_OSCBYPASS	(0x0002)
 
 /* Bit definitions and macros for CIR */
-#define CCM_CIR_PRN(x)			(((x)&0x003F))	/* Part revision number */
-#define CCM_CIR_PIN(x)			(((x)&0x03FF)<<6)	/* Part identification number */
-#define CCM_CIR_PIN_MASK		(0xFFC0)
-#define CCM_CIR_PRN_MASK		(0x003F)
+#define CCM_CIR_PIN(x)			(((x) & 0xFFC0) >> 6)
+#define CCM_CIR_PRN(x)			((x) & 0x003F)
 #define CCM_CIR_PIN_MCF52277		(0x0000)
 
 /* Bit definitions and macros for MISCCR */
@@ -195,7 +193,7 @@
 * General Purpose I/O Module (GPIO)
 *********************************************************************/
 /* Bit definitions and macros for PAR_BE */
-#define GPIO_PAR_BE_MASK		(0x0F)
+#define GPIO_PAR_BE_UNMASK		(0x0F)
 #define GPIO_PAR_BE_BE3_BE3		(0x08)
 #define GPIO_PAR_BE_BE3_GPIO		(0x00)
 #define GPIO_PAR_BE_BE2_BE2		(0x04)
@@ -217,111 +215,111 @@
 #define GPIO_PAR_FBCTL_OE		(0x80)
 #define GPIO_PAR_FBCTL_TA		(0x40)
 #define GPIO_PAR_FBCTL_RW		(0x20)
-#define GPIO_PAR_FBCTL_TS_MASK		(0xE7)
+#define GPIO_PAR_FBCTL_TS_UNMASK	(0xE7)
 #define GPIO_PAR_FBCTL_TS_FBTS		(0x18)
 #define GPIO_PAR_FBCTL_TS_DMAACK	(0x10)
 #define GPIO_PAR_FBCTL_TS_GPIO		(0x00)
 
 /* Bit definitions and macros for PAR_FECI2C */
-#define GPIO_PAR_I2C_SCL_MASK		(0xF3)
+#define GPIO_PAR_I2C_SCL_UNMASK		(0xF3)
 #define GPIO_PAR_I2C_SCL_SCL		(0x0C)
 #define GPIO_PAR_I2C_SCL_CANTXD		(0x08)
 #define GPIO_PAR_I2C_SCL_U2TXD		(0x04)
 #define GPIO_PAR_I2C_SCL_GPIO		(0x00)
 
-#define GPIO_PAR_I2C_SDA_MASK		(0xFC)
+#define GPIO_PAR_I2C_SDA_UNMASK		(0xFC)
 #define GPIO_PAR_I2C_SDA_SDA		(0x03)
 #define GPIO_PAR_I2C_SDA_CANRXD		(0x02)
 #define GPIO_PAR_I2C_SDA_U2RXD		(0x01)
 #define GPIO_PAR_I2C_SDA_GPIO		(0x00)
 
 /* Bit definitions and macros for PAR_UART */
-#define GPIO_PAR_UART_U1CTS_MASK	(0x3FFF)
+#define GPIO_PAR_UART_U1CTS_UNMASK	(0x3FFF)
 #define GPIO_PAR_UART_U1CTS_U1CTS	(0xC000)
 #define GPIO_PAR_UART_U1CTS_SSIBCLK	(0x8000)
 #define GPIO_PAR_UART_U1CTS_LCDCLS	(0x4000)
 #define GPIO_PAR_UART_U1CTS_GPIO	(0x0000)
 
-#define GPIO_PAR_UART_U1RTS_MASK	(0xCFFF)
+#define GPIO_PAR_UART_U1RTS_UNMASK	(0xCFFF)
 #define GPIO_PAR_UART_U1RTS_U1RTS	(0x3000)
 #define GPIO_PAR_UART_U1RTS_SSIFS	(0x2000)
 #define GPIO_PAR_UART_U1RTS_LCDPS	(0x1000)
 #define GPIO_PAR_UART_U1RTS_GPIO	(0x0000)
 
-#define GPIO_PAR_UART_U1RXD_MASK	(0xF3FF)
+#define GPIO_PAR_UART_U1RXD_UNMASK	(0xF3FF)
 #define GPIO_PAR_UART_U1RXD_U1RXD	(0x0C00)
 #define GPIO_PAR_UART_U1RXD_SSIRXD	(0x0800)
 #define GPIO_PAR_UART_U1RXD_GPIO	(0x0000)
 
-#define GPIO_PAR_UART_U1TXD_MASK	(0xFCFF)
+#define GPIO_PAR_UART_U1TXD_UNMASK	(0xFCFF)
 #define GPIO_PAR_UART_U1TXD_U1TXD	(0x0300)
 #define GPIO_PAR_UART_U1TXD_SSITXD	(0x0200)
 #define GPIO_PAR_UART_U1TXD_GPIO	(0x0000)
 
-#define GPIO_PAR_UART_U0CTS_MASK	(0xFF3F)
+#define GPIO_PAR_UART_U0CTS_UNMASK	(0xFF3F)
 #define GPIO_PAR_UART_U0CTS_U0CTS	(0x00C0)
 #define GPIO_PAR_UART_U0CTS_T1OUT	(0x0080)
 #define GPIO_PAR_UART_U0CTS_USBVBUSEN	(0x0040)
 #define GPIO_PAR_UART_U0CTS_GPIO	(0x0000)
 
-#define GPIO_PAR_UART_U0RTS_MASK	(0xFFCF)
+#define GPIO_PAR_UART_U0RTS_UNMASK	(0xFFCF)
 #define GPIO_PAR_UART_U0RTS_U0RTS	(0x0030)
 #define GPIO_PAR_UART_U0RTS_T1IN	(0x0020)
 #define GPIO_PAR_UART_U0RTS_USBVBUSOC	(0x0010)
 #define GPIO_PAR_UART_U0RTS_GPIO	(0x0000)
 
-#define GPIO_PAR_UART_U0RXD_MASK	(0xFFF3)
+#define GPIO_PAR_UART_U0RXD_UNMASK	(0xFFF3)
 #define GPIO_PAR_UART_U0RXD_U0RXD	(0x000C)
 #define GPIO_PAR_UART_U0RXD_CANRX	(0x0008)
 #define GPIO_PAR_UART_U0RXD_GPIO	(0x0000)
 
-#define GPIO_PAR_UART_U0TXD_MASK	(0xFFFC)
+#define GPIO_PAR_UART_U0TXD_UNMASK	(0xFFFC)
 #define GPIO_PAR_UART_U0TXD_U0TXD	(0x0003)
 #define GPIO_PAR_UART_U0TXD_CANTX	(0x0002)
 #define GPIO_PAR_UART_U0TXD_GPIO	(0x0000)
 
 /* Bit definitions and macros for PAR_DSPI */
-#define GPIO_PAR_DSPI_PCS0_MASK		(0x3F)
+#define GPIO_PAR_DSPI_PCS0_UNMASK	(0x3F)
 #define GPIO_PAR_DSPI_PCS0_PCS0		(0xC0)
 #define GPIO_PAR_DSPI_PCS0_U2RTS	(0x80)
 #define GPIO_PAR_DSPI_PCS0_GPIO		(0x00)
-#define GPIO_PAR_DSPI_SIN_MASK		(0xCF)
+#define GPIO_PAR_DSPI_SIN_UNMASK	(0xCF)
 #define GPIO_PAR_DSPI_SIN_SIN		(0x30)
 #define GPIO_PAR_DSPI_SIN_U2RXD		(0x20)
 #define GPIO_PAR_DSPI_SIN_GPIO		(0x00)
-#define GPIO_PAR_DSPI_SOUT_MASK		(0xF3)
+#define GPIO_PAR_DSPI_SOUT_UNMASK	(0xF3)
 #define GPIO_PAR_DSPI_SOUT_SOUT		(0x0C)
 #define GPIO_PAR_DSPI_SOUT_U2TXD	(0x08)
 #define GPIO_PAR_DSPI_SOUT_GPIO		(0x00)
-#define GPIO_PAR_DSPI_SCK_MASK		(0xFC)
+#define GPIO_PAR_DSPI_SCK_UNMASK	(0xFC)
 #define GPIO_PAR_DSPI_SCK_SCK		(0x03)
 #define GPIO_PAR_DSPI_SCK_U2CTS		(0x02)
 #define GPIO_PAR_DSPI_SCK_GPIO		(0x00)
 
 /* Bit definitions and macros for PAR_TIMER */
-#define GPIO_PAR_TIMER_T3IN_MASK	(0x3F)
+#define GPIO_PAR_TIMER_T3IN_UNMASK	(0x3F)
 #define GPIO_PAR_TIMER_T3IN_T3IN	(0xC0)
 #define GPIO_PAR_TIMER_T3IN_T3OUT	(0x80)
 #define GPIO_PAR_TIMER_T3IN_SSIMCLK	(0x40)
 #define GPIO_PAR_TIMER_T3IN_GPIO	(0x00)
-#define GPIO_PAR_TIMER_T2IN_MASK	(0xCF)
+#define GPIO_PAR_TIMER_T2IN_UNMASK	(0xCF)
 #define GPIO_PAR_TIMER_T2IN_T2IN	(0x30)
 #define GPIO_PAR_TIMER_T2IN_T2OUT	(0x20)
 #define GPIO_PAR_TIMER_T2IN_DSPIPCS2	(0x10)
 #define GPIO_PAR_TIMER_T2IN_GPIO	(0x00)
-#define GPIO_PAR_TIMER_T1IN_MASK	(0xF3)
+#define GPIO_PAR_TIMER_T1IN_UNMASK	(0xF3)
 #define GPIO_PAR_TIMER_T1IN_T1IN	(0x0C)
 #define GPIO_PAR_TIMER_T1IN_T1OUT	(0x08)
 #define GPIO_PAR_TIMER_T1IN_LCDCONTRAST	(0x04)
 #define GPIO_PAR_TIMER_T1IN_GPIO	(0x00)
-#define GPIO_PAR_TIMER_T0IN_MASK	(0xFC)
+#define GPIO_PAR_TIMER_T0IN_UNMASK	(0xFC)
 #define GPIO_PAR_TIMER_T0IN_T0IN	(0x03)
 #define GPIO_PAR_TIMER_T0IN_T0OUT	(0x02)
 #define GPIO_PAR_TIMER_T0IN_LCDREV	(0x01)
 #define GPIO_PAR_TIMER_T0IN_GPIO	(0x00)
 
 /* Bit definitions and macros for GPIO_PAR_LCDCTL */
-#define GPIO_PAR_LCDCTL_ACDOE_MASK	(0xE7)
+#define GPIO_PAR_LCDCTL_ACDOE_UNMASK	(0xE7)
 #define GPIO_PAR_LCDCTL_ACDOE_ACDOE	(0x18)
 #define GPIO_PAR_LCDCTL_ACDOE_SPLSPR	(0x10)
 #define GPIO_PAR_LCDCTL_ACDOE_GPIO	(0x00)
@@ -330,141 +328,141 @@
 #define GPIO_PAR_LCDCTL_LSCLK		(0x01)
 
 /* Bit definitions and macros for PAR_IRQ */
-#define GPIO_PAR_IRQ_IRQ4_MASK		(0xF3)
+#define GPIO_PAR_IRQ_IRQ4_UNMASK	(0xF3)
 #define GPIO_PAR_IRQ_IRQ4_SSIINPCLK	(0x0C)
 #define GPIO_PAR_IRQ_IRQ4_DMAREQ0	(0x08)
 #define GPIO_PAR_IRQ_IRQ4_GPIO		(0x00)
-#define GPIO_PAR_IRQ_IRQ1_MASK		(0xFC)
+#define GPIO_PAR_IRQ_IRQ1_UNMASK	(0xFC)
 #define GPIO_PAR_IRQ_IRQ1_PCIINT	(0x03)
 #define GPIO_PAR_IRQ_IRQ1_USBCLKIN	(0x02)
 #define GPIO_PAR_IRQ_IRQ1_SSICLKIN	(0x01)
 #define GPIO_PAR_IRQ_IRQ1_GPIO		(0x00)
 
 /* Bit definitions and macros for GPIO_PAR_LCDH */
-#define GPIO_PAR_LCDH_LD17_MASK		(0xFFFFF3FF)
+#define GPIO_PAR_LCDH_LD17_UNMASK	(0xFFFFF3FF)
 #define GPIO_PAR_LCDH_LD17_LD17		(0x00000C00)
 #define GPIO_PAR_LCDH_LD17_LD11		(0x00000800)
 #define GPIO_PAR_LCDH_LD17_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDH_LD16_MASK		(0xFFFFFCFF)
+#define GPIO_PAR_LCDH_LD16_UNMASK	(0xFFFFFCFF)
 #define GPIO_PAR_LCDH_LD16_LD16		(0x00000300)
 #define GPIO_PAR_LCDH_LD16_LD10		(0x00000200)
 #define GPIO_PAR_LCDH_LD16_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDH_LD15_MASK		(0xFFFFFF3F)
+#define GPIO_PAR_LCDH_LD15_UNMASK	(0xFFFFFF3F)
 #define GPIO_PAR_LCDH_LD15_LD15		(0x000000C0)
 #define GPIO_PAR_LCDH_LD15_LD9		(0x00000080)
 #define GPIO_PAR_LCDH_LD15_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDH_LD14_MASK		(0xFFFFFFCF)
+#define GPIO_PAR_LCDH_LD14_UNMASK	(0xFFFFFFCF)
 #define GPIO_PAR_LCDH_LD14_LD14		(0x00000030)
 #define GPIO_PAR_LCDH_LD14_LD8		(0x00000020)
 #define GPIO_PAR_LCDH_LD14_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDH_LD13_MASK		(0xFFFFFFF3)
+#define GPIO_PAR_LCDH_LD13_UNMASK	(0xFFFFFFF3)
 #define GPIO_PAR_LCDH_LD13_LD13		(0x0000000C)
 #define GPIO_PAR_LCDH_LD13_CANTX	(0x00000008)
 #define GPIO_PAR_LCDH_LD13_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDH_LD12_MASK		(0xFFFFFFFC)
+#define GPIO_PAR_LCDH_LD12_UNMASK	(0xFFFFFFFC)
 #define GPIO_PAR_LCDH_LD12_LD12		(0x00000003)
 #define GPIO_PAR_LCDH_LD12_CANRX	(0x00000002)
 #define GPIO_PAR_LCDH_LD12_GPIO		(0x00000000)
 
 /* Bit definitions and macros for GPIO_PAR_LCDL */
-#define GPIO_PAR_LCDL_LD11_MASK		(0x3FFFFFFF)
+#define GPIO_PAR_LCDL_LD11_UNMASK	(0x3FFFFFFF)
 #define GPIO_PAR_LCDL_LD11_LD11		(0xC0000000)
 #define GPIO_PAR_LCDL_LD11_LD7		(0x80000000)
 #define GPIO_PAR_LCDL_LD11_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDL_LD10_MASK		(0xCFFFFFFF)
+#define GPIO_PAR_LCDL_LD10_UNMASK	(0xCFFFFFFF)
 #define GPIO_PAR_LCDL_LD10_LD10		(0x30000000)
 #define GPIO_PAR_LCDL_LD10_LD6		(0x20000000)
 #define GPIO_PAR_LCDL_LD10_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDL_LD9_MASK		(0xF3FFFFFF)
+#define GPIO_PAR_LCDL_LD9_UNMASK	(0xF3FFFFFF)
 #define GPIO_PAR_LCDL_LD9_LD9		(0x0C000000)
 #define GPIO_PAR_LCDL_LD9_LD5		(0x08000000)
 #define GPIO_PAR_LCDL_LD9_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDL_LD8_MASK		(0xFCFFFFFF)
+#define GPIO_PAR_LCDL_LD8_UNMASK	(0xFCFFFFFF)
 #define GPIO_PAR_LCDL_LD8_LD8		(0x03000000)
 #define GPIO_PAR_LCDL_LD8_LD4		(0x02000000)
 #define GPIO_PAR_LCDL_LD8_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDL_LD7_MASK		(0xFF3FFFFF)
+#define GPIO_PAR_LCDL_LD7_UNMASK	(0xFF3FFFFF)
 #define GPIO_PAR_LCDL_LD7_LD7		(0x00C00000)
 #define GPIO_PAR_LCDL_LD7_PWM7		(0x00800000)
 #define GPIO_PAR_LCDL_LD7_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDL_LD6_MASK		(0xFFCFFFFF)
+#define GPIO_PAR_LCDL_LD6_UNMASK	(0xFFCFFFFF)
 #define GPIO_PAR_LCDL_LD6_LD6		(0x00300000)
 #define GPIO_PAR_LCDL_LD6_PWM5		(0x00200000)
 #define GPIO_PAR_LCDL_LD6_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDL_LD5_MASK		(0xFFF3FFFF)
+#define GPIO_PAR_LCDL_LD5_UNMASK	(0xFFF3FFFF)
 #define GPIO_PAR_LCDL_LD5_LD5		(0x000C0000)
 #define GPIO_PAR_LCDL_LD5_LD3		(0x00080000)
 #define GPIO_PAR_LCDL_LD5_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDL_LD4_MASK		(0xFFFCFFFF)
+#define GPIO_PAR_LCDL_LD4_UNMASK	(0xFFFCFFFF)
 #define GPIO_PAR_LCDL_LD4_LD4		(0x00030000)
 #define GPIO_PAR_LCDL_LD4_LD2		(0x00020000)
 #define GPIO_PAR_LCDL_LD4_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDL_LD3_MASK		(0xFFFF3FFF)
+#define GPIO_PAR_LCDL_LD3_UNMASK	(0xFFFF3FFF)
 #define GPIO_PAR_LCDL_LD3_LD3		(0x0000C000)
 #define GPIO_PAR_LCDL_LD3_LD1		(0x00008000)
 #define GPIO_PAR_LCDL_LD3_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDL_LD2_MASK		(0xFFFFCFFF)
+#define GPIO_PAR_LCDL_LD2_UNMASK	(0xFFFFCFFF)
 #define GPIO_PAR_LCDL_LD2_LD2		(0x00003000)
 #define GPIO_PAR_LCDL_LD2_LD0		(0x00002000)
 #define GPIO_PAR_LCDL_LD2_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDL_LD1_MASK		(0xFFFFF3FF)
+#define GPIO_PAR_LCDL_LD1_UNMASK	(0xFFFFF3FF)
 #define GPIO_PAR_LCDL_LD1_LD1		(0x00000C00)
 #define GPIO_PAR_LCDL_LD1_PWM3		(0x00000800)
 #define GPIO_PAR_LCDL_LD1_GPIO		(0x00000000)
 
-#define GPIO_PAR_LCDL_LD0_MASK		(0xFFFFFCFF)
+#define GPIO_PAR_LCDL_LD0_UNMASK	(0xFFFFFCFF)
 #define GPIO_PAR_LCDL_LD0_LD0		(0x00000300)
 #define GPIO_PAR_LCDL_LD0_PWM1		(0x00000200)
 #define GPIO_PAR_LCDL_LD0_GPIO		(0x00000000)
 
 /* Bit definitions and macros for MSCR_FB */
-#define GPIO_MSCR_FB_DUPPER_MASK	(0xCF)
+#define GPIO_MSCR_FB_DUPPER_UNMASK	(0xCF)
 #define GPIO_MSCR_FB_DUPPER_25V_33V	(0x30)
 #define GPIO_MSCR_FB_DUPPER_FULL_18V	(0x20)
 #define GPIO_MSCR_FB_DUPPER_OD		(0x10)
 #define GPIO_MSCR_FB_DUPPER_HALF_18V	(0x00)
 
-#define GPIO_MSCR_FB_DLOWER_MASK	(0xF3)
+#define GPIO_MSCR_FB_DLOWER_UNMASK	(0xF3)
 #define GPIO_MSCR_FB_DLOWER_25V_33V	(0x0C)
 #define GPIO_MSCR_FB_DLOWER_FULL_18V	(0x08)
 #define GPIO_MSCR_FB_DLOWER_OD		(0x04)
 #define GPIO_MSCR_FB_DLOWER_HALF_18V	(0x00)
 
-#define GPIO_MSCR_FB_ADDRCTL_MASK	(0xFC)
+#define GPIO_MSCR_FB_ADDRCTL_UNMASK	(0xFC)
 #define GPIO_MSCR_FB_ADDRCTL_25V_33V	(0x03)
 #define GPIO_MSCR_FB_ADDRCTL_FULL_18V	(0x02)
 #define GPIO_MSCR_FB_ADDRCTL_OD		(0x01)
 #define GPIO_MSCR_FB_ADDRCTL_HALF_18V	(0x00)
 
 /* Bit definitions and macros for MSCR_SDRAM */
-#define GPIO_MSCR_SDRAM_SDCLKB_MASK	(0xCF)
+#define GPIO_MSCR_SDRAM_SDCLKB_UNMASK	(0xCF)
 #define GPIO_MSCR_SDRAM_SDCLKB_25V_33V	(0x30)
 #define GPIO_MSCR_SDRAM_SDCLKB_FULL_18V	(0x20)
 #define GPIO_MSCR_SDRAM_SDCLKB_OD	(0x10)
 #define GPIO_MSCR_SDRAM_SDCLKB_HALF_18V	(0x00)
 
-#define GPIO_MSCR_SDRAM_SDCLK_MASK	(0xF3)
+#define GPIO_MSCR_SDRAM_SDCLK_UNMASK	(0xF3)
 #define GPIO_MSCR_SDRAM_SDCLK_25V_33V	(0x0C)
 #define GPIO_MSCR_SDRAM_SDCLK_FULL_18V	(0x08)
 #define GPIO_MSCR_SDRAM_SDCLK_OPD	(0x04)
 #define GPIO_MSCR_SDRAM_SDCLK_HALF_18V	(0x00)
 
-#define GPIO_MSCR_SDRAM_SDCTL_MASK	(0xFC)
+#define GPIO_MSCR_SDRAM_SDCTL_UNMASK	(0xFC)
 #define GPIO_MSCR_SDRAM_SDCTL_25V_33V	(0x03)
 #define GPIO_MSCR_SDRAM_SDCTL_FULL_18V	(0x02)
 #define GPIO_MSCR_SDRAM_SDCTL_OPD	(0x01)