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authorWolfgang Denk <wd@denx.de>2010-03-28 00:04:18 +0100
committerWolfgang Denk <wd@denx.de>2010-03-28 00:04:18 +0100
commitbe1a91320ce0cb7330bb650d1576bb56c55092af (patch)
treef6bb6d34565d4f5b3386a23885fb3df6c17e0456 /include/asm-m68k/m520x.h
parent6b94b4962211c16ee2197048faa887e1f92f3757 (diff)
parent9d3a86aec52cb3c0e9badd12167d9292184ce4dd (diff)
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Merge branch 'next' of git://git.denx.de/u-boot-coldfire into next
Diffstat (limited to 'include/asm-m68k/m520x.h')
-rw-r--r--include/asm-m68k/m520x.h89
1 files changed, 44 insertions, 45 deletions
diff --git a/include/asm-m68k/m520x.h b/include/asm-m68k/m520x.h
index 267bfd9..71f147e 100644
--- a/include/asm-m68k/m520x.h
+++ b/include/asm-m68k/m520x.h
@@ -70,7 +70,6 @@
#define PACR_TP 1
#define SCM_BMT_BME (0x00000008)
-#define SCM_BMT_BMT_MASK (0x07)
#define SCM_BMT_BMT(x) ((x) & 0x07)
#define SCM_BMT_BMT1024 (0x0000)
#define SCM_BMT_BMT512 (0x0001)
@@ -179,7 +178,7 @@
#define CCM_CCR_PLL_MODE (0x0002)
#define CCM_CCR_RESERVED (0x0001)
-#define CCM_CIR_PIN(x) (((x) & 0x03FF) << 6)
+#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6)
#define CCM_CIR_PRN(x) ((x) & 0x003F)
/* *** General Purpose I/O (GPIO) *** */
@@ -196,7 +195,7 @@
#define GPIO_PAR_FBCTL_OE (0x10)
#define GPIO_PAR_FBCTL_TA (0x08)
#define GPIO_PAR_FBCTL_RWB (0x04)
-#define GPIO_PAR_FBCTL_TS_MASK (0xFC)
+#define GPIO_PAR_FBCTL_TS_UNMASK (0xFC)
#define GPIO_PAR_FBCTL_TS_TS (0x03)
#define GPIO_PAR_FBCTL_TS_DMA (0x02)
@@ -207,39 +206,39 @@
#define GPIO_PAR_CS3 (0x08)
#define GPIO_PAR_CS2 (0x04)
-#define GPIO_PAR_CS1_MASK (0xFC)
+#define GPIO_PAR_CS1_UNMASK (0xFC)
#define GPIO_PAR_CS1_CS1 (0x03)
#define GPIO_PAR_CS1_SDCS1 (0x02)
-#define GPIO_PAR_FECI2C_RMII_MASK (0x0F)
-#define GPIO_PAR_FECI2C_MDC_MASK (0x3F)
+#define GPIO_PAR_FECI2C_RMII_UNMASK (0x0F)
+#define GPIO_PAR_FECI2C_MDC_UNMASK (0x3F)
#define GPIO_PAR_FECI2C_MDC_MDC (0xC0)
#define GPIO_PAR_FECI2C_MDC_SCL (0x80)
#define GPIO_PAR_FECI2C_MDC_U2TXD (0x40)
-#define GPIO_PAR_FECI2C_MDIO_MASK (0xCF)
+#define GPIO_PAR_FECI2C_MDIO_UNMASK (0xCF)
#define GPIO_PAR_FECI2C_MDIO_MDIO (0x30)
#define GPIO_PAR_FECI2C_MDIO_SDA (0x20)
#define GPIO_PAR_FECI2C_MDIO_U2RXD (0x10)
-#define GPIO_PAR_FECI2C_I2C_MASK (0xF0)
-#define GPIO_PAR_FECI2C_SCL_MASK (0xF3)
+#define GPIO_PAR_FECI2C_I2C_UNMASK (0xF0)
+#define GPIO_PAR_FECI2C_SCL_UNMASK (0xF3)
#define GPIO_PAR_FECI2C_SCL_SCL (0x0C)
#define GPIO_PAR_FECI2C_SCL_U2RXD (0x04)
-#define GPIO_PAR_FECI2C_SDA_MASK (0xFC)
+#define GPIO_PAR_FECI2C_SDA_UNMASK (0xFC)
#define GPIO_PAR_FECI2C_SDA_SDA (0x03)
#define GPIO_PAR_FECI2C_SDA_U2TXD (0x01)
-#define GPIO_PAR_QSPI_PCS2_MASK (0x3F)
+#define GPIO_PAR_QSPI_PCS2_UNMASK (0x3F)
#define GPIO_PAR_QSPI_PCS2_PCS2 (0xC0)
#define GPIO_PAR_QSPI_PCS2_DACK0 (0x80)
#define GPIO_PAR_QSPI_PCS2_U2RTS (0x40)
-#define GPIO_PAR_QSPI_DIN_MASK (0xCF)
+#define GPIO_PAR_QSPI_DIN_UNMASK (0xCF)
#define GPIO_PAR_QSPI_DIN_DIN (0x30)
#define GPIO_PAR_QSPI_DIN_DREQ0 (0x20)
#define GPIO_PAR_QSPI_DIN_U2CTS (0x10)
-#define GPIO_PAR_QSPI_DOUT_MASK (0xF3)
+#define GPIO_PAR_QSPI_DOUT_UNMASK (0xF3)
#define GPIO_PAR_QSPI_DOUT_DOUT (0x0C)
#define GPIO_PAR_QSPI_DOUT_SDA (0x08)
-#define GPIO_PAR_QSPI_SCK_MASK (0xFC)
+#define GPIO_PAR_QSPI_SCK_UNMASK (0xFC)
#define GPIO_PAR_QSPI_SCK_SCK (0x03)
#define GPIO_PAR_QSPI_SCK_SCL (0x02)
@@ -247,50 +246,50 @@
#define GPIO_PAR_TMR_TIN2(x) (((x) & 0x03) << 4)
#define GPIO_PAR_TMR_TIN1(x) (((x) & 0x03) << 2)
#define GPIO_PAR_TMR_TIN0(x) ((x) & 0x03)
-#define GPIO_PAR_TMR_TIN3_MASK (0x3F)
+#define GPIO_PAR_TMR_TIN3_UNMASK (0x3F)
#define GPIO_PAR_TMR_TIN3_TIN3 (0xC0)
#define GPIO_PAR_TMR_TIN3_TOUT3 (0x80)
#define GPIO_PAR_TMR_TIN3_U2CTS (0x40)
-#define GPIO_PAR_TMR_TIN2_MASK (0xCF)
+#define GPIO_PAR_TMR_TIN2_UNMASK (0xCF)
#define GPIO_PAR_TMR_TIN2_TIN2 (0x30)
#define GPIO_PAR_TMR_TIN2_TOUT2 (0x20)
#define GPIO_PAR_TMR_TIN2_U2RTS (0x10)
-#define GPIO_PAR_TMR_TIN1_MASK (0xF3)
+#define GPIO_PAR_TMR_TIN1_UNMASK (0xF3)
#define GPIO_PAR_TMR_TIN1_TIN1 (0x0C)
#define GPIO_PAR_TMR_TIN1_TOUT1 (0x08)
#define GPIO_PAR_TMR_TIN1_U2RXD (0x04)
-#define GPIO_PAR_TMR_TIN0_MASK (0xFC)
+#define GPIO_PAR_TMR_TIN0_UNMASK (0xFC)
#define GPIO_PAR_TMR_TIN0_TIN0 (0x03)
#define GPIO_PAR_TMR_TIN0_TOUT0 (0x02)
#define GPIO_PAR_TMR_TIN0_U2TXD (0x01)
-#define GPIO_PAR_UART1_MASK (0xF03F)
-#define GPIO_PAR_UART0_MASK (0xFFC0)
-#define GPIO_PAR_UART_U1CTS_MASK (0xF3FF)
+#define GPIO_PAR_UART1_UNMASK (0xF03F)
+#define GPIO_PAR_UART0_UNMASK (0xFFC0)
+#define GPIO_PAR_UART_U1CTS_UNMASK (0xF3FF)
#define GPIO_PAR_UART_U1CTS_U1CTS (0x0C00)
#define GPIO_PAR_UART_U1CTS_TIN1 (0x0800)
#define GPIO_PAR_UART_U1CTS_PCS1 (0x0400)
-#define GPIO_PAR_UART_U1RTS_MASK (0xFCFF)
+#define GPIO_PAR_UART_U1RTS_UNMASK (0xFCFF)
#define GPIO_PAR_UART_U1RTS_U1RTS (0x0300)
#define GPIO_PAR_UART_U1RTS_TOUT1 (0x0200)
#define GPIO_PAR_UART_U1RTS_PCS1 (0x0100)
#define GPIO_PAR_UART_U1TXD (0x0080)
#define GPIO_PAR_UART_U1RXD (0x0040)
-#define GPIO_PAR_UART_U0CTS_MASK (0xFFCF)
+#define GPIO_PAR_UART_U0CTS_UNMASK (0xFFCF)
#define GPIO_PAR_UART_U0CTS_U0CTS (0x0030)
#define GPIO_PAR_UART_U0CTS_TIN0 (0x0020)
#define GPIO_PAR_UART_U0CTS_PCS0 (0x0010)
-#define GPIO_PAR_UART_U0RTS_MASK (0xFFF3)
+#define GPIO_PAR_UART_U0RTS_UNMASK (0xFFF3)
#define GPIO_PAR_UART_U0RTS_U0RTS (0x000C)
#define GPIO_PAR_UART_U0RTS_TOUT0 (0x0008)
#define GPIO_PAR_UART_U0RTS_PCS0 (0x0004)
#define GPIO_PAR_UART_U0TXD (0x0002)
#define GPIO_PAR_UART_U0RXD (0x0001)
-#define GPIO_PAR_FEC_7W_MASK (0xF3)
+#define GPIO_PAR_FEC_7W_UNMASK (0xF3)
#define GPIO_PAR_FEC_7W_FEC (0x0C)
#define GPIO_PAR_FEC_7W_U1RTS (0x04)
-#define GPIO_PAR_FEC_MII_MASK (0xFC)
+#define GPIO_PAR_FEC_MII_UNMASK (0xFC)
#define GPIO_PAR_FEC_MII_FEC (0x03)
#define GPIO_PAR_FEC_MII_UnCTS (0x01)
@@ -300,17 +299,17 @@
#define GPIO_MSCR_FB_DUP(x) (((x) & 0x03) << 4)
#define GPIO_MSCR_FB_DLO(x) (((x) & 0x03) << 2)
#define GPIO_MSCR_FB_ADRCTL(x) ((x) & 0x03)
-#define GPIO_MSCR_FB_FBCLK_MASK (0x3F)
-#define GPIO_MSCR_FB_DUP_MASK (0xCF)
-#define GPIO_MSCR_FB_DLO_MASK (0xF3)
-#define GPIO_MSCR_FB_ADRCTL_MASK (0xFC)
+#define GPIO_MSCR_FB_FBCLK_UNMASK (0x3F)
+#define GPIO_MSCR_FB_DUP_UNMASK (0xCF)
+#define GPIO_MSCR_FB_DLO_UNMASK (0xF3)
+#define GPIO_MSCR_FB_ADRCTL_UNMASK (0xFC)
#define GPIO_MSCR_SDR_SDCLKB(x) (((x) & 0x03) << 4)
#define GPIO_MSCR_SDR_SDCLK(x) (((x) & 0x03) << 2)
#define GPIO_MSCR_SDR_SDRAM(x) ((x) & 0x03)
-#define GPIO_MSCR_SDR_SDCLKB_MASK (0xCF)
-#define GPIO_MSCR_SDR_SDCLK_MASK (0xF3)
-#define GPIO_MSCR_SDR_SDRAM_MASK (0xFC)
+#define GPIO_MSCR_SDR_SDCLKB_UNMASK (0xCF)
+#define GPIO_MSCR_SDR_SDCLK_UNMASK (0xF3)
+#define GPIO_MSCR_SDR_SDRAM_UNMASK (0xFC)
#define MSCR_25VDDR (0x03)
#define MSCR_18VDDR_FULL (0x02)
@@ -318,27 +317,27 @@
#define MSCR_18VDDR_HALF (0x00)
#define GPIO_DSCR_I2C(x) ((x) & 0x03)
-#define GPIO_DSCR_I2C_MASK (0xFC)
+#define GPIO_DSCR_I2C_UNMASK (0xFC)
#define GPIO_DSCR_MISC_DBG(x) (((x) & 0x03) << 4)
-#define GPIO_DSCR_MISC_DBG_MASK (0xCF)
+#define GPIO_DSCR_MISC_DBG_UNMASK (0xCF)
#define GPIO_DSCR_MISC_RSTOUT(x) (((x) & 0x03) << 2)
-#define GPIO_DSCR_MISC_RSTOUT_MASK (0xF3)
+#define GPIO_DSCR_MISC_RSTOUT_UNMASK (0xF3)
#define GPIO_DSCR_MISC_TIMER(x) ((x) & 0x03)
-#define GPIO_DSCR_MISC_TIMER_MASK (0xFC)
+#define GPIO_DSCR_MISC_TIMER_UNMASK (0xFC)
#define GPIO_DSCR_FEC(x) ((x) & 0x03)
-#define GPIO_DSCR_FEC_MASK (0xFC)
+#define GPIO_DSCR_FEC_UNMASK (0xFC)
#define GPIO_DSCR_UART_UART1(x) (((x) & 0x03) << 4)
-#define GPIO_DSCR_UART_UART1_MASK (0xCF)
+#define GPIO_DSCR_UART_UART1_UNMASK (0xCF)
#define GPIO_DSCR_UART_UART0(x) (((x) & 0x03) << 2)
-#define GPIO_DSCR_UART_UART0_MASK (0xF3)
+#define GPIO_DSCR_UART_UART0_UNMASK (0xF3)
#define GPIO_DSCR_UART_IRQ(x) ((x) & 0x03)
-#define GPIO_DSCR_UART_IRQ_MASK (0xFC)
+#define GPIO_DSCR_UART_IRQ_UNMASK (0xFC)
#define GPIO_DSCR_QSPI(x) ((x) & 0x03)
-#define GPIO_DSCR_QSPI_MASK (0xFC)
+#define GPIO_DSCR_QSPI_UNMASK (0xFC)
#define DSCR_50PF (0x03)
#define DSCR_30PF (0x02)
@@ -347,12 +346,12 @@
/* *** Phase Locked Loop (PLL) *** */
#define PLL_PODR_CPUDIV(x) (((x) & 0x0F) << 4)
-#define PLL_PODR_CPUDIV_MASK (0x0F)
+#define PLL_PODR_CPUDIV_UNMASK (0x0F)
#define PLL_PODR_BUSDIV(x) ((x) & 0x0F)
-#define PLL_PODR_BUSDIV_MASK (0xF0)
+#define PLL_PODR_BUSDIV_UNMASK (0xF0)
#define PLL_PCR_DITHEN (0x80)
#define PLL_PCR_DITHDEV(x) ((x) & 0x07)
-#define PLL_PCR_DITHDEV_MASK (0xF8)
+#define PLL_PCR_DITHDEV_UNMASK (0xF8)
#endif /* __M520X__ */